Module atsam4lc8c::pdca
[−]
[src]
Peripheral DMA Controller
Modules
cr |
Control Register |
idr |
Interrupt Disable Register |
ier |
Interrupt Enable Register |
imr |
Interrupt Mask Register |
isr |
Interrupt Status Register |
mar |
Memory Address Register |
marr |
Memory Address Reload Register |
mr |
Mode Register |
pcontrol |
Performance Control Register |
prdata0 |
Channel 0 Read Data Cycles |
prdata1 |
Channel 1 Read Data Cycles |
prlat0 |
Channel 0 Read Max Latency |
prlat1 |
Channel 1 Read Max Latency |
prstall0 |
Channel 0 Read Stall Cycles |
prstall1 |
Channel Read Stall Cycles |
psr |
Peripheral Select Register |
pwdata0 |
Channel 0 Write Data Cycles |
pwdata1 |
Channel 1 Write Data Cycles |
pwlat0 |
Channel0 Write Max Latency |
pwlat1 |
Channel 1 Read Max Latency |
pwstall0 |
Channel 0 Write Stall Cycles |
pwstall1 |
Channel 1 Write stall Cycles |
sr |
Status Register |
tcr |
Transfer Counter Register |
tcrr |
Transfer Counter Reload Register |
version |
Version Register |
Structs
CR |
Control Register |
IDR |
Interrupt Disable Register |
IER |
Interrupt Enable Register |
IMR |
Interrupt Mask Register |
ISR |
Interrupt Status Register |
MAR |
Memory Address Register |
MARR |
Memory Address Reload Register |
MR |
Mode Register |
PCONTROL |
Performance Control Register |
PRDATA0 |
Channel 0 Read Data Cycles |
PRDATA1 |
Channel 1 Read Data Cycles |
PRLAT0 |
Channel 0 Read Max Latency |
PRLAT1 |
Channel 1 Read Max Latency |
PRSTALL0 |
Channel 0 Read Stall Cycles |
PRSTALL1 |
Channel Read Stall Cycles |
PSR |
Peripheral Select Register |
PWDATA0 |
Channel 0 Write Data Cycles |
PWDATA1 |
Channel 1 Write Data Cycles |
PWLAT0 |
Channel0 Write Max Latency |
PWLAT1 |
Channel 1 Read Max Latency |
PWSTALL0 |
Channel 0 Write Stall Cycles |
PWSTALL1 |
Channel 1 Write stall Cycles |
RegisterBlock |
Register block |
SR |
Status Register |
TCR |
Transfer Counter Register |
TCRR |
Transfer Counter Reload Register |
VERSION |
Version Register |