Struct atsam4e8c_pac::dmac::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 38 fields
pub gcfg: GCFG,
pub en: EN,
pub sreq: SREQ,
pub creq: CREQ,
pub last: LAST,
pub ebcier: EBCIER,
pub ebcidr: EBCIDR,
pub ebcimr: EBCIMR,
pub ebcisr: EBCISR,
pub cher: CHER,
pub chdr: CHDR,
pub chsr: CHSR,
pub saddr0: SADDR0,
pub daddr0: DADDR0,
pub dscr0: DSCR0,
pub ctrla0: CTRLA0,
pub ctrlb0: CTRLB0,
pub cfg0: CFG0,
pub saddr1: SADDR1,
pub daddr1: DADDR1,
pub dscr1: DSCR1,
pub ctrla1: CTRLA1,
pub ctrlb1: CTRLB1,
pub cfg1: CFG1,
pub saddr2: SADDR2,
pub daddr2: DADDR2,
pub dscr2: DSCR2,
pub ctrla2: CTRLA2,
pub ctrlb2: CTRLB2,
pub cfg2: CFG2,
pub saddr3: SADDR3,
pub daddr3: DADDR3,
pub dscr3: DSCR3,
pub ctrla3: CTRLA3,
pub ctrlb3: CTRLB3,
pub cfg3: CFG3,
pub wpmr: WPMR,
pub wpsr: WPSR,
/* private fields */
}
Expand description
Register block
Fields§
§gcfg: GCFG
0x00 - DMAC Global Configuration Register
en: EN
0x04 - DMAC Enable Register
sreq: SREQ
0x08 - DMAC Software Single Request Register
creq: CREQ
0x0c - DMAC Software Chunk Transfer Request Register
last: LAST
0x10 - DMAC Software Last Transfer Flag Register
ebcier: EBCIER
0x18 - DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.
ebcidr: EBCIDR
0x1c - DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.
ebcimr: EBCIMR
0x20 - DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.
ebcisr: EBCISR
0x24 - DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.
cher: CHER
0x28 - DMAC Channel Handler Enable Register
chdr: CHDR
0x2c - DMAC Channel Handler Disable Register
chsr: CHSR
0x30 - DMAC Channel Handler Status Register
saddr0: SADDR0
0x3c - DMAC Channel Source Address Register (ch_num = 0)
daddr0: DADDR0
0x40 - DMAC Channel Destination Address Register (ch_num = 0)
dscr0: DSCR0
0x44 - DMAC Channel Descriptor Address Register (ch_num = 0)
ctrla0: CTRLA0
0x48 - DMAC Channel Control A Register (ch_num = 0)
ctrlb0: CTRLB0
0x4c - DMAC Channel Control B Register (ch_num = 0)
cfg0: CFG0
0x50 - DMAC Channel Configuration Register (ch_num = 0)
saddr1: SADDR1
0x64 - DMAC Channel Source Address Register (ch_num = 1)
daddr1: DADDR1
0x68 - DMAC Channel Destination Address Register (ch_num = 1)
dscr1: DSCR1
0x6c - DMAC Channel Descriptor Address Register (ch_num = 1)
ctrla1: CTRLA1
0x70 - DMAC Channel Control A Register (ch_num = 1)
ctrlb1: CTRLB1
0x74 - DMAC Channel Control B Register (ch_num = 1)
cfg1: CFG1
0x78 - DMAC Channel Configuration Register (ch_num = 1)
saddr2: SADDR2
0x8c - DMAC Channel Source Address Register (ch_num = 2)
daddr2: DADDR2
0x90 - DMAC Channel Destination Address Register (ch_num = 2)
dscr2: DSCR2
0x94 - DMAC Channel Descriptor Address Register (ch_num = 2)
ctrla2: CTRLA2
0x98 - DMAC Channel Control A Register (ch_num = 2)
ctrlb2: CTRLB2
0x9c - DMAC Channel Control B Register (ch_num = 2)
cfg2: CFG2
0xa0 - DMAC Channel Configuration Register (ch_num = 2)
saddr3: SADDR3
0xb4 - DMAC Channel Source Address Register (ch_num = 3)
daddr3: DADDR3
0xb8 - DMAC Channel Destination Address Register (ch_num = 3)
dscr3: DSCR3
0xbc - DMAC Channel Descriptor Address Register (ch_num = 3)
ctrla3: CTRLA3
0xc0 - DMAC Channel Control A Register (ch_num = 3)
ctrlb3: CTRLB3
0xc4 - DMAC Channel Control B Register (ch_num = 3)
cfg3: CFG3
0xc8 - DMAC Channel Configuration Register (ch_num = 3)
wpmr: WPMR
0x1e4 - DMAC Write Protect Mode Register
wpsr: WPSR
0x1e8 - DMAC Write Protect Status Register