Expand description
Per-VM Arm virtual Generic Interrupt Controller.
The crate owns guest architectural interrupt state. Host GIC discovery, guest firmware, VM scheduling, and bus registration remain in the AArch64 AxVM integration. GICv2 and GICv3 frontends share the same canonical state owner; the host CPU-interface implementation is a checked backend.
Structs§
- Assigned
SpiConfig - One physical SPI binding fixed before controller creation.
- Collection
Id - ITS collection identifier.
- CpuInterface
State - Complete ICH state saved for one vCPU.
- EventId
- ITS event identifier.
- GicAffinity
- Four-level GIC affinity.
- GicV3
Backend Error - Backend-specific failure without leaking a platform error type.
- GicV3
Config - Complete configuration for one VM-local GICv3 controller.
- GicV3
Controller - One VM-local GICv3 controller.
- GicV3
Hardware Capabilities - Validated capabilities reported by a physical GICv3 Distributor.
- GicV3
Mmio Region - One guest-visible MMIO register frame.
- GicV3
Vcpu Binding - Per-vCPU lifecycle handle returned by
GicV3Controller::attach_vcpu. - GicVcpu
Id - VM-local vCPU identifier used by the controller.
- Guest
Memory Error - Guest-memory capability failure.
- ItsConfig
- One guest-visible ITS instance.
- ItsDevice
Id - ITS device identifier.
- List
Register State - One virtual interrupt represented in an ICH list register.
- LpiId
- Locality-specific peripheral interrupt identifier.
- Physical
Interrupt Binding - Explicit guest-to-physical SPI ownership.
- Physical
IrqId - Platform-owned physical interrupt identifier.
- Physical
MsiBinding - Explicit VM-owned physical ITS translation.
- PpiId
- Private peripheral interrupt identifier.
- Priority
- Interrupt priority, where a lower numeric value has higher priority.
- SgiId
- Software-generated interrupt identifier.
- Software
GicV3 Backend - Backend for software-only tests and architecture-neutral emulation.
- SpiId
- Shared peripheral interrupt identifier.
- Vgic
Backend Capabilities - Normalized host virtual interrupt-interface capabilities.
- Vgic
Core - The single canonical virtual interrupt-controller state owner for one VM.
- Vgic
Device Set - Complete set of bus devices exposing one
VgicCore. - Vgic
V2Config - Complete GICv2 configuration for one VM.
- Vgic
V3Config - Complete GICv3 configuration for one VM.
Enums§
- ArmVgic
Config - Versioned immutable VGIC configuration.
- GicV3
SpiOwnership - Policy describing which SPIs are visible through the guest Distributor.
- Host
GicVersion - Host virtual CPU-interface architecture implemented by a backend.
- IntId
- A validated GICv3 interrupt identifier.
- Interrupt
State - GIC interrupt lifecycle state.
- List
Register Backing - Source backing used for one virtual list-register delivery.
- Register
Region - GICv3 register block involved in an access.
- SgiTarget
- Target selection for one SGI operation.
- Trigger
Mode - Electrical trigger behavior for a wired interrupt.
- Vgic
Error - Errors reported by the virtual GICv3 model.
Constants§
- LPI_
INTID_ BASE - First architectural LPI INTID.
- LPI_
INTID_ MAX - Highest INTID representable by GICv3 LPIs.
Traits§
- GicV3
Backend - Version-neutral name used by the unified VGIC core. Platform operations required by a GICv3 controller.
- GicV3
Vcpu Wake - Runtime wake capability associated with one attached vCPU.
- Guest
Memory - Checked access to memory owned by one guest VM.
- Vgic
Backend - Version-neutral name used by the unified VGIC core. Platform operations required by a GICv3 controller.
Type Aliases§
- Vgic
Controller - Version-neutral canonical VGIC controller used by architecture frontends.
- Vgic
Mmio Region - One sanitized guest-visible register region.
- Vgic
Result - Result returned by GICv3 domain operations.