[−][src]Module ambiq_apollo3p_pac::pwrctrl::mempwreventen
Event enable register to control which MEMPWRSTATUS bits are routed to event input of CPU.
Structs
| CACHEB0EN_W | Write proxy for field |
| CACHEB2EN_W | Write proxy for field |
| DTCMEN_W | Write proxy for field |
| FLASH0EN_W | Write proxy for field |
| FLASH1EN_W | Write proxy for field |
| SRAMEN_W | Write proxy for field |
Enums
| CACHEB0EN_A | Control CACHE BANK 0 power-on status event |
| CACHEB2EN_A | Control CACHEB2 power-on status event |
| DTCMEN_A | Enable DTCM power-on status event |
| FLASH0EN_A | Control FLASH power-on status event |
| FLASH1EN_A | Control FLASH power-on status event |
| SRAMEN_A | Control SRAM power-on status event |
Type Definitions
| CACHEB0EN_R | Reader of field |
| CACHEB2EN_R | Reader of field |
| DTCMEN_R | Reader of field |
| FLASH0EN_R | Reader of field |
| FLASH1EN_R | Reader of field |
| R | Reader of register MEMPWREVENTEN |
| SRAMEN_R | Reader of field |
| W | Writer for register MEMPWREVENTEN |