Module ambiq_apollo3p_pac::pwrctrl::mempwren

Enables individual banks of the MEMORY array

Structs

CACHEB0_W	Write proxy for field CACHEB0
CACHEB2_W	Write proxy for field CACHEB2
DTCM_W	Write proxy for field DTCM
FLASH0_W	Write proxy for field FLASH0
FLASH1_W	Write proxy for field FLASH1
SRAM_W	Write proxy for field SRAM

Enums

CACHEB0_A	Power up Cache Bank 0. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 0, cache has to be enabled and this bit has to be set.
CACHEB2_A	Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 2, cache has to be enabled and this bit has to be set.
DTCM_A	Power up DTCM
FLASH0_A	Power up FLASH group 0 (0MB-1MB)
FLASH1_A	Power up FLASH group 1 (1MB-2MB)
SRAM_A	Power up SRAM groups

Type Definitions

CACHEB0_R	Reader of field CACHEB0
CACHEB2_R	Reader of field CACHEB2
DTCM_R	Reader of field DTCM
FLASH0_R	Reader of field FLASH0
FLASH1_R	Reader of field FLASH1
R	Reader of register MEMPWREN
SRAM_R	Reader of field SRAM
W	Writer for register MEMPWREN