Module ambiq_apollo3p_pac::mcuctrl

MCU Miscellaneous Control Logic

Modules

adcbattload	ADC Battery Load Enable
adccal	ADC Calibration Control
adcpwrdly	ADC Power Up Delay Control
adcrefcomp	ADC Reference Keeper and Comparator Control
adctrim	ADC Trims
blebuck2	BLEBUCK2 Control Reg
bootloader	Bootloader and secure boot functions
chipid0	Unique Chip ID 0
chipid1	Unique Chip ID 1
chippn	Chip Information Register
chiprev	Chip Revision
dbgr1	Read-only debug register 1
dbgr2	Read-only debug register 2
dcodefaultaddr	DCODE bus address which was present when a bus fault occurred.
debugger	Debugger Control
dmasramreadprotect0	SRAM read-protection bits.
dmasramreadprotect1	SRAM read-protection bits.
dmasramreadprotect2	SRAM read-protection bits.
dmasramwriteprotect0	SRAM write-protection bits.
dmasramwriteprotect1	SRAM write-protection bits.
dmasramwriteprotect2	SRAM write-protection bits.
faultcaptureen	Enable the fault capture registers
faultstatus	Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.
featureenable	Feature Enable on Burst and BLE
flashrprot0	Flash Read Protection Bits
flashrprot1	Flash Read Protection Bits
flashrprot2	Flash Read Protection Bits
flashrprot3	Flash Read Protection Bits
flashwprot0	Flash Write Protection Bits
flashwprot1	Flash Write Protection Bits
flashwprot2	Flash Write Protection Bits
flashwprot3	Flash Write Protection Bits
icodefaultaddr	ICODE bus address which was present when a bus fault occurred.
kextclksel	Key Register to enable the use of external clock selects via the EXTCLKSEL reg
miscctrl	Miscellaneous control register.
otapointer	OTA (Over the Air) Update Pointer/Status. Reset only by POA
pmuenable	Control bit to enable/disable the PMU
scratch0	Scratch register that is not reset by any reset
scratch1	Scratch register that is not reset by any reset
shadowvalid	Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.
simobuck2	SIMO Buck Control Reg 2
simobuck3	SIMO Buck Control Reg 3
simobuck4	SIMO Buck Control Reg 4
sku	Unique Chip SKU
srammode	SRAM Controller mode bits
sysfaultaddr	System bus address which was present when a bus fault occurred.
tpiuctrl	TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.
vendorid	Unique Vendor ID
xtalctrl	XTAL Oscillator Control
xtalgenctrl	XTAL Oscillator General Control

Structs

RegisterBlock

Register block

Type Definitions

ADCBATTLOAD	ADC Battery Load Enable
ADCCAL	ADC Calibration Control
ADCPWRDLY	ADC Power Up Delay Control
ADCREFCOMP	ADC Reference Keeper and Comparator Control
ADCTRIM	ADC Trims
BLEBUCK2	BLEBUCK2 Control Reg
BOOTLOADER	Bootloader and secure boot functions
CHIPID0	Unique Chip ID 0
CHIPID1	Unique Chip ID 1
CHIPPN	Chip Information Register
CHIPREV	Chip Revision
DBGR1	Read-only debug register 1
DBGR2	Read-only debug register 2
DCODEFAULTADDR	DCODE bus address which was present when a bus fault occurred.
DEBUGGER	Debugger Control
DMASRAMREADPROTECT0	SRAM read-protection bits.
DMASRAMREADPROTECT1	SRAM read-protection bits.
DMASRAMREADPROTECT2	SRAM read-protection bits.
DMASRAMWRITEPROTECT0	SRAM write-protection bits.
DMASRAMWRITEPROTECT1	SRAM write-protection bits.
DMASRAMWRITEPROTECT2	SRAM write-protection bits.
FAULTCAPTUREEN	Enable the fault capture registers
FAULTSTATUS	Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.
FEATUREENABLE	Feature Enable on Burst and BLE
FLASHRPROT0	Flash Read Protection Bits
FLASHRPROT1	Flash Read Protection Bits
FLASHRPROT2	Flash Read Protection Bits
FLASHRPROT3	Flash Read Protection Bits
FLASHWPROT0	Flash Write Protection Bits
FLASHWPROT1	Flash Write Protection Bits
FLASHWPROT2	Flash Write Protection Bits
FLASHWPROT3	Flash Write Protection Bits
ICODEFAULTADDR	ICODE bus address which was present when a bus fault occurred.
KEXTCLKSEL	Key Register to enable the use of external clock selects via the EXTCLKSEL reg
MISCCTRL	Miscellaneous control register.
OTAPOINTER	OTA (Over the Air) Update Pointer/Status. Reset only by POA
PMUENABLE	Control bit to enable/disable the PMU
SCRATCH0	Scratch register that is not reset by any reset
SCRATCH1	Scratch register that is not reset by any reset
SHADOWVALID	Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.
SIMOBUCK2	SIMO Buck Control Reg 2
SIMOBUCK3	SIMO Buck Control Reg 3
SIMOBUCK4	SIMO Buck Control Reg 4
SKU	Unique Chip SKU
SRAMMODE	SRAM Controller mode bits
SYSFAULTADDR	System bus address which was present when a bus fault occurred.
TPIUCTRL	TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.
VENDORID	Unique Vendor ID
XTALCTRL	XTAL Oscillator Control
XTALGENCTRL	XTAL Oscillator General Control