[−][src]Module ambiq_apollo3p_pac::bleif
BLE Interface
Modules
| blecfg | BLE Core Control |
| bledbg | BLEIF Master Debug Register |
| bstatus | BLE Core status |
| clkcfg | I/O Clock Configuration |
| cmd | Command and offset Register |
| cmdrpt | Command Repeat Register |
| cmdstat | Command status |
| cqaddr | CQ Target Read Address Register |
| cqcfg | Command Queue Configuration Register |
| cqcuridx | IOM Command Queue current index value. Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue |
| cqendidx | IOM Command Queue current index value. Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue |
| cqflags | Command Queue Flag Register |
| cqpauseen | Command Queue Pause Enable Register |
| cqsetclear | Command Queue Flag Set/Clear Register |
| cqstat | Command Queue Status Register |
| dmacfg | DMA Configuration Register |
| dmastat | DMA Status Register |
| dmatargaddr | DMA Target Address Register |
| dmatotcount | DMA Total Transfer Count |
| dmatrigen | DMA Trigger Enable Register |
| dmatrigstat | DMA Trigger Status Register |
| fifo | FIFO Access Port |
| fifoctrl | FIFO Control Register |
| fifoloc | FIFO Pointers |
| fifopop | FIFO POP register |
| fifoptr | FIFO size and remaining slots open values |
| fifopush | FIFO PUSH register |
| fifothr | FIFO Threshold Configuration |
| intclr | IO Master Interrupts: Clear |
| inten | IO Master Interrupts: Enable |
| intset | IO Master Interrupts: Set |
| intstat | IO Master Interrupts: Status |
| mspicfg | SPI module master configuration |
| offsethi | High order offset bytes |
| pwrcmd | BLE Power command interface |
| status | IOM Module Status Register |
Structs
| RegisterBlock | Register block |
Type Definitions
| BLECFG | BLE Core Control |
| BLEDBG | BLEIF Master Debug Register |
| BSTATUS | BLE Core status |
| CLKCFG | I/O Clock Configuration |
| CMD | Command and offset Register |
| CMDRPT | Command Repeat Register |
| CMDSTAT | Command status |
| CQADDR | CQ Target Read Address Register |
| CQCFG | Command Queue Configuration Register |
| CQCURIDX | IOM Command Queue current index value. Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue |
| CQENDIDX | IOM Command Queue current index value. Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue |
| CQFLAGS | Command Queue Flag Register |
| CQPAUSEEN | Command Queue Pause Enable Register |
| CQSETCLEAR | Command Queue Flag Set/Clear Register |
| CQSTAT | Command Queue Status Register |
| DMACFG | DMA Configuration Register |
| DMASTAT | DMA Status Register |
| DMATARGADDR | DMA Target Address Register |
| DMATOTCOUNT | DMA Total Transfer Count |
| DMATRIGEN | DMA Trigger Enable Register |
| DMATRIGSTAT | DMA Trigger Status Register |
| FIFO | FIFO Access Port |
| FIFOCTRL | FIFO Control Register |
| FIFOLOC | FIFO Pointers |
| FIFOPOP | FIFO POP register |
| FIFOPTR | FIFO size and remaining slots open values |
| FIFOPUSH | FIFO PUSH register |
| FIFOTHR | FIFO Threshold Configuration |
| INTCLR | IO Master Interrupts: Clear |
| INTEN | IO Master Interrupts: Enable |
| INTSET | IO Master Interrupts: Set |
| INTSTAT | IO Master Interrupts: Status |
| MSPICFG | SPI module master configuration |
| OFFSETHI | High order offset bytes |
| PWRCMD | BLE Power command interface |
| STATUS | IOM Module Status Register |