Module ambiq_apollo3_pac::pwrctrl

PWR Controller Register Bank

Modules

adcstatus	Power Status Register for ADC Block
devpwren	Device Power Enables
devpwreventen	Event enable register to control which DEVPWRSTATUS bits are routed to event input of CPU.
devpwrstatus	Device Power ON Status
mempwdinsleep	Powerdown SRAM banks in Deep Sleep mode
mempwren	Enables individual banks of the MEMORY array
mempwreventen	Event enable register to control which MEMPWRSTATUS bits are routed to event input of CPU.
mempwrstatus	Mem Power ON Status
misc	Power Optimization Control Bits
sramctrl	SRAM Control register
supplysrc	Voltage Regulator Select Register
supplystatus	Voltage Regulators status

Structs

ADCSTATUS	Power Status Register for ADC Block
DEVPWREN	Device Power Enables
DEVPWREVENTEN	Event enable register to control which DEVPWRSTATUS bits are routed to event input of CPU.
DEVPWRSTATUS	Device Power ON Status
MEMPWDINSLEEP	Powerdown SRAM banks in Deep Sleep mode
MEMPWREN	Enables individual banks of the MEMORY array
MEMPWREVENTEN	Event enable register to control which MEMPWRSTATUS bits are routed to event input of CPU.
MEMPWRSTATUS	Mem Power ON Status
MISC	Power Optimization Control Bits
RegisterBlock	Register block
SRAMCTRL	SRAM Control register
SUPPLYSRC	Voltage Regulator Select Register
SUPPLYSTATUS	Voltage Regulators status