[−][src]Module ambiq_apollo2_pac::cachectrl::cachecfg

Flash Cache Control Register

Structs

CACHE_CLKGATE_W	Write proxy for field `CACHE_CLKGATE`
CACHE_LS_W	Write proxy for field `CACHE_LS`
CONFIG_W	Write proxy for field `CONFIG`
DATA_CLKGATE_W	Write proxy for field `DATA_CLKGATE`
DCACHE_ENABLE_W	Write proxy for field `DCACHE_ENABLE`
DLY_W	Write proxy for field `DLY`
ENABLE_MONITOR_W	Write proxy for field `ENABLE_MONITOR`
ENABLE_NC0_W	Write proxy for field `ENABLE_NC0`
ENABLE_NC1_W	Write proxy for field `ENABLE_NC1`
ENABLE_W	Write proxy for field `ENABLE`
ICACHE_ENABLE_W	Write proxy for field `ICACHE_ENABLE`
LRU_W	Write proxy for field `LRU`
SERIAL_W	Write proxy for field `SERIAL`
SMDLY_W	Write proxy for field `SMDLY`

Sets the cache configuration. Only a single configuration of 0x5 is valid.

CACHE_CLKGATE_R	Reader of field `CACHE_CLKGATE`
CACHE_LS_R	Reader of field `CACHE_LS`
CONFIG_R	Reader of field `CONFIG`
DATA_CLKGATE_R	Reader of field `DATA_CLKGATE`
DCACHE_ENABLE_R	Reader of field `DCACHE_ENABLE`
DLY_R	Reader of field `DLY`
ENABLE_MONITOR_R	Reader of field `ENABLE_MONITOR`
ENABLE_NC0_R	Reader of field `ENABLE_NC0`
ENABLE_NC1_R	Reader of field `ENABLE_NC1`
ENABLE_R	Reader of field `ENABLE`
ICACHE_ENABLE_R	Reader of field `ICACHE_ENABLE`
LRU_R	Reader of field `LRU`
R	Reader of register CACHECFG
SERIAL_R	Reader of field `SERIAL`
SMDLY_R	Reader of field `SMDLY`
W	Writer for register CACHECFG