[][src]Struct ambiq_apollo1_pac::mcuctrl::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub chip_info: CHIP_INFO,
    pub chipid0: CHIPID0,
    pub chipid1: CHIPID1,
    pub chiprev: CHIPREV,
    pub supplysrc: SUPPLYSRC,
    pub supplystatus: SUPPLYSTATUS,
    pub bandgapen: BANDGAPEN,
    pub srampwdinsleep: SRAMPWDINSLEEP,
    pub srampwrdis: SRAMPWRDIS,
    pub flashpwrdis: FLASHPWRDIS,
    pub icodefaultaddr: ICODEFAULTADDR,
    pub dcodefaultaddr: DCODEFAULTADDR,
    pub sysfaultaddr: SYSFAULTADDR,
    pub faultstatus: FAULTSTATUS,
    pub faultcaptureen: FAULTCAPTUREEN,
    pub tpiuctrl: TPIUCTRL,
    // some fields omitted
}

Register block

Fields

chip_info: CHIP_INFO

0x00 - Chip Information Register

chipid0: CHIPID0

0x04 - Unique Chip ID 0

chipid1: CHIPID1

0x08 - Unique Chip ID 1

chiprev: CHIPREV

0x0c - Chip Revision

supplysrc: SUPPLYSRC

0x10 - Memory and Core Voltage Supply Source Select Register

supplystatus: SUPPLYSTATUS

0x14 - Memory and Core Voltage Supply Source Status Register

bandgapen: BANDGAPEN

0xfc - Band Gap Enable

srampwdinsleep: SRAMPWDINSLEEP

0x140 - Powerdown an SRAM Bank in Deep Sleep mode

srampwrdis: SRAMPWRDIS

0x144 - Disables individual banks of the SRAM array

flashpwrdis: FLASHPWRDIS

0x148 - Disables individual banks of the Flash array

icodefaultaddr: ICODEFAULTADDR

0x1c0 - ICODE bus address which was present when a bus fault occurred.

dcodefaultaddr: DCODEFAULTADDR

0x1c4 - DCODE bus address which was present when a bus fault occurred.

sysfaultaddr: SYSFAULTADDR

0x1c8 - System bus address which was present when a bus fault occurred.

faultstatus: FAULTSTATUS

0x1cc - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.

faultcaptureen: FAULTCAPTUREEN

0x1d0 - Enable the fault capture registers

tpiuctrl: TPIUCTRL

0x250 - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

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