Module ambiq_apollo1_pac::adc::sl3cfg

Slot 3 Configuration Register

Structs

ADSEL3_W	Write proxy for field ADSEL3
CHSEL3_W	Write proxy for field CHSEL3
SLEN3_W	Write proxy for field SLEN3
THSEL3_W	Write proxy for field THSEL3
WCEN3_W	Write proxy for field WCEN3

Enums

ADSEL3_A	Select the number of measurements to average in the accumulate divide module for this slot.
CHSEL3_A	Select one of the 13 channel inputs for this slot.
SLEN3_A	This bit enables slot 3 for ADC conversions.
THSEL3_A	Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.
WCEN3_A	This bit enables the window compare function for slot 3.

Type Definitions

ADSEL3_R	Reader of field ADSEL3
CHSEL3_R	Reader of field CHSEL3
R	Reader of register SL3CFG
SLEN3_R	Reader of field SLEN3
THSEL3_R	Reader of field THSEL3
W	Writer for register SL3CFG
WCEN3_R	Reader of field WCEN3