[−][src]Module ambiq_apollo1_pac::adc::sl0cfg
Slot 0 Configuration Register
Structs
| ADSEL0_W | Write proxy for field |
| CHSEL0_W | Write proxy for field |
| SLEN0_W | Write proxy for field |
| THSEL0_W | Write proxy for field |
| WCEN0_W | Write proxy for field |
Enums
| ADSEL0_A | Select the number of measurements to average in the accumulate divide module for this slot. |
| CHSEL0_A | Select one of the 13 channel inputs for this slot. |
| SLEN0_A | This bit enables slot 0 for ADC conversions. |
| THSEL0_A | Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks. |
| WCEN0_A | This bit enables the window compare function for slot 0. |
Type Definitions
| ADSEL0_R | Reader of field |
| CHSEL0_R | Reader of field |
| R | Reader of register SL0CFG |
| SLEN0_R | Reader of field |
| THSEL0_R | Reader of field |
| W | Writer for register SL0CFG |
| WCEN0_R | Reader of field |