#[repr(u8)]
pub enum OC1M_A {
    FROZEN,
    ACTIVEONMATCH,
    INACTIVEONMATCH,
    TOGGLE,
    FORCEINACTIVE,
    FORCEACTIVE,
    PWMMODE1,
    PWMMODE2,
}
Expand description

Output Compare 1 mode

Value on reset: 0

Variants

FROZEN

0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive

ACTIVEONMATCH

1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1

INACTIVEONMATCH

2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved

TOGGLE

3: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved

FORCEINACTIVE

4: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF

FORCEACTIVE

5: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF

PWMMODE1

6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down

PWMMODE2

7: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

Trait Implementations

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