This controls whether the reference of a group of DACs is buffered or unbuffered. The reference of the first group of DACs (A, B, C, and D) is controlled by setting Bit 2, and the second group of DACs (E, F, G, and H) is controlled by setting Bit 3.
The gain of the DACs is controlled by setting Bit 4 for the first group of DACs (A, B, C, and D) and Bit 5 for the second group of DACs (E, F, G, and H).
LDAC mode controls LDAC, which determines when data is transferred from the input registers to the DAC registers. There are three options when updating the DAC registers, as shown in Table 8 (DS p17). If the user wishes to update the DAC through software, the LDAC pin should be tied high and the LDAC mode bits set as required. Alternatively, if the user wishes to control the DAC through hardware, that is, the LDAC pin, the LDAC mode bits should be set to LDAC high (default mode).
These bits are set when VDD is to be used as a reference. The first group of DACs (A, B, C, and D) can be set up to use VDD by setting Bit 0, and the second group of DACs (E, F, G, and H) by setting Bit 1. The VDD bits have priority over the BUF bits. When VDD is used as the reference, it is always unbuffered and has an output range of 0 V to VREF regardless of the state of the GAIN and BUF bits.