Module aarch64_paging::paging

source ·
Expand description

Generic aarch64 page table manipulation functionality which doesn’t assume anything about how addresses are mapped.

Structs

  • Attributes
    Attribute bits for a mapping in a page table.
  • Constraints
    Constraints on page table mappings
  • Descriptor
    An entry in a page table.
  • MemoryRegion
    A range of virtual addresses which may be mapped in a page table.
  • PageTable
    A single level of a page table.
  • PhysicalAddress
    An aarch64 physical address or intermediate physical address, the output type of a stage 1 page table.
  • RootTable
    A complete hierarchy of page tables including all levels.
  • VirtualAddress
    An aarch64 virtual address, the input type of a stage 1 page table.

Enums

  • VaRange
    Which virtual address range a page table is for, i.e. which TTBR register to use for it.

Constants

  • BITS_PER_LEVEL
    The number of address bits resolved in one level of page table lookup. This is a function of the page size.
  • PAGE_SIZE
    The page size in bytes assumed by this library, 4 KiB.

Traits

  • Translation
    An implementation of this trait needs to be provided to the mapping routines, so that the physical addresses used in the page tables can be converted into virtual addresses that can be used to access their contents from the code.