Crate aarch64_paging

source ·
Expand description

A library to manipulate AArch64 VMSA page tables.

Currently it only supports:

  • stage 1 page tables
  • EL1
  • 4 KiB pages

Full support is provided for identity mapping (IdMap) and linear mapping (LinearMap). If you want to use a different mapping scheme, you must provide an implementation of the Translation trait and then use Mapping directly.

Example

use aarch64_paging::{
    idmap::IdMap,
    paging::{Attributes, MemoryRegion},
};

const ASID: usize = 1;
const ROOT_LEVEL: usize = 1;

// Create a new page table with identity mapping.
let mut idmap = IdMap::new(ASID, ROOT_LEVEL);
// Map a 2 MiB region of memory as read-write.
idmap.map_range(
    &MemoryRegion::new(0x80200000, 0x80400000),
    Attributes::NORMAL | Attributes::NON_GLOBAL | Attributes::VALID,
).unwrap();
// SAFETY: Everything the program uses is within the 2 MiB region mapped above.
unsafe {
    // Set `TTBR0_EL1` to activate the page table.
    idmap.activate();
}

Modules

  • idmap
    Functionality for managing page tables with identity mapping.
  • linearmap
    Functionality for managing page tables with linear mapping.
  • paging
    Generic aarch64 page table manipulation functionality which doesn’t assume anything about how addresses are mapped.

Structs

  • Mapping
    Manages a level 1 page table and associated state.

Enums

  • MapError
    An error attempting to map some range in the page table.