aarch64_cpu/registers/sctlr_el2.rs
1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6// - Andre Richter <andre.o.richter@gmail.com>
7// - Bradley Landherr <landhb@users.noreply.github.com>
8
9//! System Control Register - EL2
10//!
11//! Provides top level control of the system, including its memory system, at EL2.
12
13use tock_registers::{
14 interfaces::{Readable, Writeable},
15 register_bitfields,
16};
17
18register_bitfields! {u64,
19 pub SCTLR_EL2 [
20
21 /// Exception endianness. The possible values are:
22 ///
23 /// 0 Little endian.
24 /// 1 Big endian.
25 EE OFFSET(25) NUMBITS(1) [
26 Little = 0,
27 Big = 1
28 ],
29
30 /// When FEAT_ExS is implemented control if taking an exception to EL2 is a context
31 /// synchonizing event
32 EIS OFFSET(22) NUMBITS(1) [
33 IsNotSynch = 0,
34 IsSynch = 1
35 ],
36
37 /// When FEAT_IESB is implemented control if an implict ESB is added at each exception
38 /// and before each ERET to/from EL2
39 IESB OFFSET(21) NUMBITS(1) [
40 Disable = 0,
41 Enable = 1
42 ],
43
44 /// Force treatment of all memory regions with write permissions as XN.
45 /// The possible values are:
46 ///
47 /// 0 Regions with write permissions are not forced XN. This is the reset value.
48 /// 1 Regions with write permissions are forced XN.
49 WXN OFFSET(19) NUMBITS(1) [
50 Disable = 0,
51 Enable = 1
52 ],
53
54 /// Instruction Cache Control, two possible values:
55 ///
56 /// 0 All instruction access to Normal memory from EL2 are Non-cacheable for all
57 /// levels of instruction and unified cache.
58 ///
59 /// If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2 or EL2&0
60 /// translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer
61 /// Non-cacheable memory.
62 ///
63 /// 1 This control has no effect on the Cacheability of instruction access to Normal memory
64 /// from EL2 and, when EL2 is enabled in the current Security state and
65 /// HCR_EL2.{E2H, TGE} == {1, 1}, instruction access to Normal memory from EL0.
66 ///
67 /// If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2&0
68 /// translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer
69 /// Write-Through memory.
70 ///
71 /// When EL2 is disabled, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit
72 /// has no effect on the PE.
73 ///
74 /// On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.
75 I OFFSET(12) NUMBITS(1) [
76 NonCacheable = 0,
77 Cacheable = 1
78 ],
79
80 /// When FEAT_ExS is implemented Exception exit is a context synchronization event.
81 EOS OFFSET(11) NUMBITS(1) [
82 IsNotSynch = 0,
83 IsSynch = 1
84 ],
85
86 /// SP Alignment check enable.
87 ///
88 /// When set to 1, if a load or store instruction executed at EL2 uses the SP
89 /// as the base address and the SP is not aligned to a 16-byte boundary,
90 /// then a SP alignment fault exception is generated.
91 SA OFFSET(3) NUMBITS(1) [
92 Disable = 0,
93 Enable = 1
94 ],
95
96 /// Cacheability control, for data accesses.
97 ///
98 /// 0 The following are Non-cacheable for all levels of data and unified cache:
99 /// - Data accesses to Normal memory from EL2.
100 /// - When HCR_EL2.{E2H, TGE} != {1, 1}, Normal memory accesses to the EL2 translation tables.
101 /// - When EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}:
102 /// - Data accesses to Normal memory from EL0.
103 /// - Normal memory accesses to the EL2&0 translation tables.
104 ///
105 /// 1 This control has no effect on the Cacheability of:
106 /// - Data access to Normal memory from EL2.
107 /// - When HCR_EL2.{E2H, TGE} != {1, 1}, Normal memory accesses to the EL2 translation tables.
108 /// - When EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}:
109 /// - Data accesses to Normal memory from EL0.
110 /// - Normal memory accesses to the EL2&0 translation tables.
111 ///
112 /// When EL2 is disabled in the current Security state or HCR_EL2.{E2H, TGE} != {1, 1},
113 /// this bit has no effect on the EL1&0 translation regime.
114 ///
115 /// On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.
116 C OFFSET(2) NUMBITS(1) [
117 NonCacheable = 0,
118 Cacheable = 1
119 ],
120
121 /// Alignment check enable. This is the enable bit for Alignment fault checking at EL2 and,
122 /// when EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}, EL0.
123 ///
124 /// Instructions that load or store one or more registers, other than load/store exclusive
125 /// and load-acquire/store-release, will or will not check that the address being accessed
126 /// is aligned to the size of the data element(s) being accessed depending on this flag.
127 ///
128 /// Load/store exclusive and load-acquire/store-release instructions have an alignment check
129 /// regardless of the value of the A bit.
130 A OFFSET(1) NUMBITS(1) [
131 Disable = 0,
132 Enable = 1
133 ],
134
135 /// MMU enable for EL2 or EL2&0 stage 1 address translation. Possible values of this bit are:
136 ///
137 /// 0 - When HCR_EL2.{E2H, TGE} != {1, 1}, EL2 stage 1 address translation disabled.
138 /// - When HCR_EL2.{E2H, TGE} == {1, 1}, EL2&0 stage 1 address translation disabled.
139 /// - See the SCTLR_EL2.I field for the behavior of instruction accesses to Normal memory.
140 ///
141 /// 1 - When HCR_EL2.{E2H, TGE} != {1, 1}, EL2 stage 1 address translation enabled.
142 /// - When HCR_EL2.{E2H, TGE} == {1, 1}, EL2&0 stage 1 address translation enabled.
143 ///
144 /// On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.
145 M OFFSET(0) NUMBITS(1) [
146 Disable = 0,
147 Enable = 1
148 ]
149 ]
150}
151
152pub struct Reg;
153
154impl Readable for Reg {
155 type T = u64;
156 type R = SCTLR_EL2::Register;
157
158 sys_coproc_read_raw!(u64, "SCTLR_EL2", "x");
159}
160
161impl Writeable for Reg {
162 type T = u64;
163 type R = SCTLR_EL2::Register;
164
165 sys_coproc_write_raw!(u64, "SCTLR_EL2", "x");
166}
167
168pub const SCTLR_EL2: Reg = Reg {};