Module rk3399_pac::sdmmc
source · Expand description
Secure Digital MultiMedia Card (SDMMC) Registers
Modules§
- Back-end power register
- Block-size register
- Bus mode register
- Current buffer descriptor address register
- Byte-count register
- Card read threshold enable register
- Card-detect register
- Clock-divider register
- Clock-enable register
- SD clock source register
- Command register
- Command-argument register
- Control register
- Card-type register
- Descriptor list base address register
- Card detect debounce register
- Current host descriptor address register
- eMMC4.5 DDR start bit detection control register
- FIFO base address register
- FIFO threshold register
- Hardware configuration register
- Internal DMAC interrupt enable register
- Internal DMAC status register
- Interrupt-mask register
- Masked interrupt-status register
- Poll demand register
- Power-enable register
- Response-0 register
- Response-1 register
- Response-2 register
- Response-3 register
- Raw interrupt-status register
- Hardware reset register
- Status register
- Transferred host/DMA to/from BIU-FIFO byte count
- Transferred CIU card byte count
- Time-out register
- UHS-1 register
- User ID register
- Version ID register
- Write-protect register
Structs§
- Register block
Type Aliases§
- BACK_END_POWER (rw) register accessor: Back-end power register
- BLKSIZ (rw) register accessor: Block-size register
- BMOD (rw) register accessor: Bus mode register
- BUFADDR (rw) register accessor: Current buffer descriptor address register
- BYTCNT (rw) register accessor: Byte-count register
- CARDTHRCTL (rw) register accessor: Card read threshold enable register
- CDETECT (r) register accessor: Card-detect register
- CLKDIV (rw) register accessor: Clock-divider register
- CLKENA (rw) register accessor: Clock-enable register
- CLKSRC (rw) register accessor: SD clock source register
- CMD (rw) register accessor: Command register
- CMDARG (rw) register accessor: Command-argument register
- CTRL (rw) register accessor: Control register
- CTYPE (rw) register accessor: Card-type register
- DBADDR (rw) register accessor: Descriptor list base address register
- DEBNCE (rw) register accessor: Card detect debounce register
- DSCADDR (rw) register accessor: Current host descriptor address register
- EMMC_DDR_REG (rw) register accessor: eMMC4.5 DDR start bit detection control register
- FIFO_BASE (rw) register accessor: FIFO base address register
- FIFOTH (rw) register accessor: FIFO threshold register
- HCON (r) register accessor: Hardware configuration register
- IDINTEN (rw) register accessor: Internal DMAC interrupt enable register
- IDSTS (rw) register accessor: Internal DMAC status register
- INTMASK (rw) register accessor: Interrupt-mask register
- MINTSTS (rw) register accessor: Masked interrupt-status register
- PLDMND (w) register accessor: Poll demand register
- PWREN (rw) register accessor: Power-enable register
- RESP0 (r) register accessor: Response-0 register
- RESP1 (r) register accessor: Response-1 register
- RESP2 (r) register accessor: Response-2 register
- RESP3 (r) register accessor: Response-3 register
- RINTSTS (rw) register accessor: Raw interrupt-status register
- RST_n (rw) register accessor: Hardware reset register
- STATUS (r) register accessor: Status register
- TBBCNT (r) register accessor: Transferred host/DMA to/from BIU-FIFO byte count
- TCBCNT (r) register accessor: Transferred CIU card byte count
- TMOUT (rw) register accessor: Time-out register
- UHS_REG (rw) register accessor: UHS-1 register
- USRID (rw) register accessor: User ID register
- VERID (r) register accessor: Version ID register
- WRTPRT (rw) register accessor: Write-protect register