Module rk3399_pac::pcie_core
source · Expand description
PCIe Core Registers
Modules§
- EP Inbound BAR Address Translation 0
- EP Inbound BAR Address Translation 1
- Outbound Region Address 0
- Outbound Region Address 1
- Outbound Region Descriptor 0
- Outbound Region Descriptor 1
- Outbound Region Descriptor 2
- Outbound Region Descriptor 3
- Link down indication bit
- RP Inbound BAR Address Translation 0
- RP Inbound BAR Address Translation 1
- PCIe DMA Capability and Version Register
- PCIe DMA Channel 0 Attribute Lower Register
- PCIe DMA Channel 0 Attribute Upper Register
- PCIe DMA Channel 0 Control Register
- PCIe DMA Channel 0 Start Pointer Lower Register
- PCIe DMA Channel 0 Start Pointer Upper Register
- PCIe DMA Channel 1 Attribute Lower Register
- PCIe DMA Channel 1 Attribute Upper Register
- PCIe DMA Channel 1 Control Register
- PCIe DMA Channel 1 Start Pointer Lower Register
- PCIe DMA Channel 1 Start Pointer Upper Register
- PCIe DMA Configuration Register
- PCIe DMA Inbound Buffer corrected ECC Errors
- PCIe DMA Inbound Buffer Uncorrected ECC Errors
- PCIe DMA Interrupt Register
- PCIe DMA Interrupt Disable Register
- PCIe DMA Interrupt Enable Register
- PCIe DMA Outbound Buffer corrected ECC Errors
- PCIe DMA Outbound Buffer Uncorrected ECC Errors
- ASPM L1 Entry Timeout Delay Register
- Completion Timeout Limit Register 0
- Completion Timeout Limit Register 1
- Data Link Layer Timer Configuration Register
- Debug Mux Control Register
- ECC Correctable Error Count Register
- End Point Bus and Device Number Register
- L0S Timeout Limit Register
- L1 State Re-Entry Delay Register
- LCRC Error Count Register
- Linkwidth Control Register
- Local Error and Status Register
- Local Interrupt Mask Register
- LTR Message Generation Control Register
- LTR Snoop/No-Snoop Latency Register
- Negotiated Lane Map Register
- Physical Function BAR Configuration Register 0
- Physical Function BAR Configuration Register 1
- Physical Function Configuration Register
- Physical Layer Configuration Register 0
- Physical Layer Configuration Register 1
- PME Service Timeout Delay Register
- PME TurnOff Ack Delay Register
- Receive Credit Limit Register 0 VC0
- Receive Credit Limit Register 1 VC0
- Receive FTS Count Register
- Receive TLP Count Register
- Receive TLP Payload Dword Count Register
- Root Complex BAR Configuration Register
- Root Port Requestor ID Register
- Shadow register function number.
- Shadow register header log 0
- Shadow register header log 1
- Shadow register header log 2
- Shadow register header log 3
- Shadow Register UR Error
- SRIS Control Register
- Transmit Credit Limit Register 0 VC0
- Transmit Credit Limit Register 1 VC0
- Transmit Credit Update Interval Configuration Register 0
- Transmit Credit Update Interval Configuration Register 1
- Transmit TLP Count Register
- Transmit TLP Payload Dword Count Register
- Vendor ID Register
- Virtual Function BAR Configuration Register 0
- Virtual Function BAR Configuration Register 1
- Advanced Error Capabilities and Control Register
- Advanced Error Reporting (AER) Enhanced Capability Header Register
- ARI Capability Register and ARI Control Register
- ARI Extended Capability Header Register
- Base Address Register 0
- Base Address Register 1
- Base Address Register 2
- Base Address Register 3
- Base Address Register 4
- Base Address Register 5
- BIST, Header Type, Latency Timer and Cache Line Size Registers
- Capabilities Pointer
- Command and Status Register
- Correctable Error Mask Register
- Correctable Error Status Register
- DPA Capability Register
- DPA Control and Status Registers
- DPA Extended Capability Header Register
- DPA Latency Indicator Register
- Dynamic Power Allocation Array Register 0
- Dynamic Power Allocation Array Register 1
- Function Dependency Link/NumVFs Register
- Header Log Register 0
- Header Log Register 1
- Header Log Register 2
- Header Log Register 3
- Initial VFs/Total VFs Register
- Interrupt Line and Interrupt Pin Register
- L1 PM Substates Capabilities Register
- L1 PM Substates Control 1 Register
- L1 PM Substates Control 2 Register
- L1 PM Substates Extended Capability Header Register
- Latency Tolerance Reporting (LTR) Extended Capability Header Register
- Link Capabilities Register
- Link Capabilities Register 2
- Link Control and Status Register
- Link Control and Status Register 2
- LTR Max Snoop/Max No-Snoop Latency Register
- MSI Control Register
- MSI Mask Register
- MSI Message Data Register
- MSI Message High Address Register
- MSI Message Low Address Register
- MSI Pending Bits Register
- MSI-X Control Register
- MSI-X Pending Interrupt Register
- MSI-X Table Offset Register
- PCI Express Capability List Register
- PCI Express Device Capabilities Register
- PCI Express Device Capabilities Register 2
- PCI Express Device Control and Status Register
- PCI Express Device Control and Status Register 2
- Power Budget Capability Register
- Power Budgeting Data Register
- Power Budgeting Data Select Register
- Power Budgeting Enhanced Capability Header
- Power Management Capabilities Register
- Power Management Control/Status Report
- Resizable BAR Capability Register 0
- Resizable BAR Capability Register 1
- Resizable BAR Capability Register 2
- Resizable BAR Capability Register 3
- Resizable BAR Capability Register 4
- Resizable BAR Capability Register 5
- Resizable BAR Control Register 0
- Resizable BAR Control Register 1
- Resizable BAR Control Register 2
- Resizable BAR Control Register 3
- Resizable BAR Control Register 4
- Resizable BAR Control Register 5
- Resizable BAR Extended Capability Header Register
- Revision ID and Class Code Register
- SR-IOV Capabilities Register
- SR-IOV Control and Status Registers
- SR-IOV Extended Capability Header Register
- Subsystem Vendor ID and Subsystem ID Register
- Supported Page Sizes Register
- System Page Size Register
- TPH Requester Capability Register
- TPH Requester Control Register
- TPH Requester Extended Capability Header Register
- TPH ST Table 0
- TPH ST Table 1
- TPH ST Table 2
- TPH ST Table 3
- Uncorrectable Error Mask Register
- Uncorrectable Error Severity Register
- Uncorrectable Error Status Register
- Vendor ID and Device ID
- VF Base Address Register 0
- VF Base Address Register 1
- VF Base Address Register 2
- VF Base Address Register 3
- VF Base Address Register 4
- VF Base Address Register 5
- VF Device ID Register
- VF Migration State Array Offset Register
- VF Offset/Stride Register
- Advanced Error Capabilities and Control Register
- Advanced Error Reporting (AER) Enhanced Capability Header Register
- BIST, Header Type, Latency Timer and Cache Line Size Registers
- Capabilities Pointer
- Command and Status Register
- Correctable Error Mask Register
- Correctable Error Status Register
- Error Source Identification Register
- Header Log Register 0
- Header Log Register 1
- Header Log Register 2
- Header Log Register 3
- Interrupt Line, Interrupt Pin Register and Bridge Control Register
- IO Base, IO Limit, Secondary Status Register
- IO Base Upper, IO Limit Upper
- L1 PM Substates Capabilities Register
- L1 PM Substates Control 1 Register
- L1 PM Substates Control 2 Register
- L1 PM Substates Extended Capability Header Register
- Link Capabilities Register
- Link Capabilities Register 2
- Link Control and Status Register
- Link Control and Status 2 Register
- Memory Base, Memory Limit
- MSI Control Register
- MSI Mask Register
- MSI Message Data Register
- MSI Message High Address Register
- MSI Message Low Address Register
- MSI Pending Bits Register
- MSI-X Control Register
- MSI-X Pending Interrupt Register
- MSI-X Table Offset Register
- PCI Express Capability List Register
- PCI Express Device Capabilities Register
- PCI Express Device Capabilities 2 Register
- PCI Express Device Control and Status Register
- PCI Express Device Control and Status 2 Register
- Power Management Capabilities Register
- Power Management Control/Status Report
- Prefetchable Base Upper
- Prefetchable Limit Upper
- Prefetchable Memory Base, Prefetchable Memory Limit
- Primary Bus Number, Secondary Bus Number, Subordinate Bus Number, Secondary Latency Timer
- Revision ID and Class Code Register
- Root Complex Base Address Register 0
- Root Complex Base Address Register 1
- Root Control and Capability Register
- Root Error Command Register
- Root Error Status Register
- Root Status Register
- Slot Capability Register
- Slot Control and Status Register
- TPH ST Table 3
- Uncorrectable Error Mask Register
- Uncorrectable Error Severity Register
- Uncorrectable Error Status Register
- Vendor ID and Device ID
- Advanced Error Capabilities and Control Register
- Advanced Error Reporting (AER) Enhanced Capability Header Register
- ARI Capability Register and ARI Control Register
- ARI Extended Capability Header Register
- Base Address Register 0
- Base Address Register 1
- Base Address Register 2
- Base Address Register 3
- Base Address Register 4
- Base Address Register 5
- BIST, Header Type, Latency Timer and Cache Line Size Registers
- Capabilities Pointer
- Command and Status Register
- Correctable Error Mask Register
- Correctable Error Status Register
- Expansion ROM Base Address Register
- Header Log Register 0
- Header Log Register 1
- Header Log Register 2
- Header Log Register 3
- Interrupt Line and Interrupt Pin Register
- Link Capabilities Register
- MSI Control Register
- MSI Mask Register
- MSI Message Data Register
- MSI Message High Address Register
- MSI Message Low Address Register
- MSI Pending Bits Register
- MSI-X Control Register
- MSI-X Pending Interrupt Register
- MSI-X Table Offset Register
- PCI Express Capability List Register
- PCI Express Device Capabilities Register
- PCI Express Device Capabilities Register 2
- PCI Express Device Control and Status Register
- Power Management Capabilities Register
- Power Management Control/Status Report
- Revision ID and Class Code Register
- Subsystem Vendor ID and Subsystem ID Register
- TPH Requester Capability Register
- TPH Requester Control Register
- TPH Requester Enhanced Capability Header Register
- TPH ST Table 0
- TPH ST Table 1
- TPH ST Table 2
- Uncorrectable Error Mask Register
- Uncorrectable Error Severity Register
- Uncorrectable Error Status Register
- Vendor ID and Device ID
Structs§
- Register block
Type Aliases§
- PCIE_AT_EP_IB_EP_INBOUND_BAR_ADDRESS_TRANSLATION_0 (rw) register accessor: EP Inbound BAR Address Translation 0
- PCIE_AT_EP_IB_EP_INBOUND_BAR_ADDRESS_TRANSLATION_1 (rw) register accessor: EP Inbound BAR Address Translation 1
- PCIE_AT_OB_OUTBOUND_REGION_ADDRESS_0 (rw) register accessor: Outbound Region Address 0
- PCIE_AT_OB_OUTBOUND_REGION_ADDRESS_1 (rw) register accessor: Outbound Region Address 1
- PCIE_AT_OB_OUTBOUND_REGION_DESCRIPTOR_0 (rw) register accessor: Outbound Region Descriptor 0
- PCIE_AT_OB_OUTBOUND_REGION_DESCRIPTOR_1 (rw) register accessor: Outbound Region Descriptor 1
- PCIE_AT_OB_OUTBOUND_REGION_DESCRIPTOR_2 (rw) register accessor: Outbound Region Descriptor 2
- PCIE_AT_OB_OUTBOUND_REGION_DESCRIPTOR_3 (r) register accessor: Outbound Region Descriptor 3
- PCIE_AT_RP_IB_LINK_DOWN_INDICATION_BIT (rw) register accessor: Link down indication bit
- PCIE_AT_RP_IB_RP_INBOUND_BAR_ADDRESS_TRANSLATION_0 (rw) register accessor: RP Inbound BAR Address Translation 0
- PCIE_AT_RP_IB_RP_INBOUND_BAR_ADDRESS_TRANSLATION_1 (rw) register accessor: RP Inbound BAR Address Translation 1
- PCIE_DMA_CAPABILITY_AND_VERSION (r) register accessor: PCIe DMA Capability and Version Register
- PCIE_DMA_CHANNEL_0_ATTRIBUTE_LOWER (rw) register accessor: PCIe DMA Channel 0 Attribute Lower Register
- PCIE_DMA_CHANNEL_0_ATTRIBUTE_UPPER (rw) register accessor: PCIe DMA Channel 0 Attribute Upper Register
- PCIE_DMA_CHANNEL_0_CONTROL (rw) register accessor: PCIe DMA Channel 0 Control Register
- PCIE_DMA_CHANNEL_0_START_POINTER_LOWER (rw) register accessor: PCIe DMA Channel 0 Start Pointer Lower Register
- PCIE_DMA_CHANNEL_0_START_POINTER_UPPER (rw) register accessor: PCIe DMA Channel 0 Start Pointer Upper Register
- PCIE_DMA_CHANNEL_1_ATTRIBUTE_LOWER (rw) register accessor: PCIe DMA Channel 1 Attribute Lower Register
- PCIE_DMA_CHANNEL_1_ATTRIBUTE_UPPER (rw) register accessor: PCIe DMA Channel 1 Attribute Upper Register
- PCIE_DMA_CHANNEL_1_CONTROL (rw) register accessor: PCIe DMA Channel 1 Control Register
- PCIE_DMA_CHANNEL_1_START_POINTER_LOWER (rw) register accessor: PCIe DMA Channel 1 Start Pointer Lower Register
- PCIE_DMA_CHANNEL_1_START_POINTER_UPPER (rw) register accessor: PCIe DMA Channel 1 Start Pointer Upper Register
- PCIE_DMA_CONFIGURATION (r) register accessor: PCIe DMA Configuration Register
- PCIE_DMA_INBOUND_BUFFER_CORRECTED_ECC_ERRORS (r) register accessor: PCIe DMA Inbound Buffer corrected ECC Errors
- PCIE_DMA_INBOUND_BUFFER_UNCORRECTED_ECC_ERRORS (r) register accessor: PCIe DMA Inbound Buffer Uncorrected ECC Errors
- PCIE_DMA_INTERRUPT (rw) register accessor: PCIe DMA Interrupt Register
- PCIE_DMA_INTERRUPT_DISABLE (rw) register accessor: PCIe DMA Interrupt Disable Register
- PCIE_DMA_INTERRUPT_ENABLE (rw) register accessor: PCIe DMA Interrupt Enable Register
- PCIE_DMA_OUTBOUND_BUFFER_CORRECTED_ECC_ERRORS (r) register accessor: PCIe DMA Outbound Buffer corrected ECC Errors
- PCIE_DMA_OUTBOUND_BUFFER_UNCORRECTED_ECC_ERRORS (r) register accessor: PCIe DMA Outbound Buffer Uncorrected ECC Errors
- PCIE_LM_ASPM_L1_ENTRY_TIMEOUT_DELAY (rw) register accessor: ASPM L1 Entry Timeout Delay Register
- PCIE_LM_COMPLETION_TIMEOUT_LIMIT_0 (rw) register accessor: Completion Timeout Limit Register 0
- PCIE_LM_COMPLETION_TIMEOUT_LIMIT_1 (rw) register accessor: Completion Timeout Limit Register 1
- PCIE_LM_DATA_LINK_LAYER_TIMER_CONFIGURATION (rw) register accessor: Data Link Layer Timer Configuration Register
- PCIE_LM_DEBUG_MUX_CONTROL (rw) register accessor: Debug Mux Control Register
- PCIE_LM_ECC_CORRECTABLE_ERROR_COUNT (rw) register accessor: ECC Correctable Error Count Register
- PCIE_LM_END_POINT_BUS_AND_DEVICE_NUMBER (r) register accessor: End Point Bus and Device Number Register
- PCIE_LM_L0S_TIMEOUT_LIMIT (rw) register accessor: L0S Timeout Limit Register
- PCIE_LM_L1_STATE_RE_ENTRY_DELAY (rw) register accessor: L1 State Re-Entry Delay Register
- PCIE_LM_LCRC_ERROR_COUNT (rw) register accessor: LCRC Error Count Register
- PCIE_LM_LINKWIDTH_CONTROL (rw) register accessor: Linkwidth Control Register
- PCIE_LM_LOCAL_ERROR_AND_STATUS (rw) register accessor: Local Error and Status Register
- PCIE_LM_LOCAL_INTERRUPT_MASK (rw) register accessor: Local Interrupt Mask Register
- PCIE_LM_LTR_MESSAGE_GENERATION_CONTROL (rw) register accessor: LTR Message Generation Control Register
- PCIE_LM_LTR_SNOOP_NO_SNOOP_LATENCY (rw) register accessor: LTR Snoop/No-Snoop Latency Register
- PCIE_LM_NEGOTIATED_LANE_MAP (r) register accessor: Negotiated Lane Map Register
- PCIE_LM_PHYSICAL_FUNCTION_BAR_CONFIGURATION_0 (rw) register accessor: Physical Function BAR Configuration Register 0
- PCIE_LM_PHYSICAL_FUNCTION_BAR_CONFIGURATION_1 (rw) register accessor: Physical Function BAR Configuration Register 1
- PCIE_LM_PHYSICAL_FUNCTION_CONFIGURATION (r) register accessor: Physical Function Configuration Register
- PCIE_LM_PHYSICAL_LAYER_CONFIGURATION_0 (rw) register accessor: Physical Layer Configuration Register 0
- PCIE_LM_PHYSICAL_LAYER_CONFIGURATION_1 (rw) register accessor: Physical Layer Configuration Register 1
- PCIE_LM_PME_SERVICE_TIMEOUT_DELAY (rw) register accessor: PME Service Timeout Delay Register
- PCIE_LM_PME_TURNOFF_ACK_DELAY (rw) register accessor: PME TurnOff Ack Delay Register
- PCIE_LM_RECEIVE_CREDIT_LIMIT_0_VC0 (rw) register accessor: Receive Credit Limit Register 0 VC0
- PCIE_LM_RECEIVE_CREDIT_LIMIT_1_VC0 (rw) register accessor: Receive Credit Limit Register 1 VC0
- PCIE_LM_RECEIVE_FTS_COUNT (r) register accessor: Receive FTS Count Register
- PCIE_LM_RECEIVE_TLP_COUNT (rw) register accessor: Receive TLP Count Register
- PCIE_LM_RECEIVE_TLP_PAYLOAD_DWORD_COUNT (rw) register accessor: Receive TLP Payload Dword Count Register
- PCIE_LM_ROOT_COMPLEX_BAR_CONFIGURATION (rw) register accessor: Root Complex BAR Configuration Register
- PCIE_LM_ROOT_PORT_REQUESTOR_ID (rw) register accessor: Root Port Requestor ID Register
- PCIE_LM_SHADOW_REGISTER_FUNCTION_NUMBER (rw) register accessor: Shadow register function number.
- PCIE_LM_SHADOW_REGISTER_HEADER_LOG_0 (rw) register accessor: Shadow register header log 0
- PCIE_LM_SHADOW_REGISTER_HEADER_LOG_1 (rw) register accessor: Shadow register header log 1
- PCIE_LM_SHADOW_REGISTER_HEADER_LOG_2 (rw) register accessor: Shadow register header log 2
- PCIE_LM_SHADOW_REGISTER_HEADER_LOG_3 (rw) register accessor: Shadow register header log 3
- PCIE_LM_SHADOW_UR_ERROR (rw) register accessor: Shadow Register UR Error
- PCIE_LM_SRIS_CONTROL (rw) register accessor: SRIS Control Register
- PCIE_LM_TRANSMIT_CREDIT_LIMIT_0_VC0 (r) register accessor: Transmit Credit Limit Register 0 VC0
- PCIE_LM_TRANSMIT_CREDIT_LIMIT_1_VC0 (r) register accessor: Transmit Credit Limit Register 1 VC0
- PCIE_LM_TRANSMIT_CREDIT_UPDATE_INTERVAL_CONFIGURATION_0 (rw) register accessor: Transmit Credit Update Interval Configuration Register 0
- PCIE_LM_TRANSMIT_CREDIT_UPDATE_INTERVAL_CONFIGURATION_1 (rw) register accessor: Transmit Credit Update Interval Configuration Register 1
- PCIE_LM_TRANSMIT_TLP_COUNT (rw) register accessor: Transmit TLP Count Register
- PCIE_LM_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT (rw) register accessor: Transmit TLP Payload Dword Count Register
- PCIE_LM_VENDOR_ID (rw) register accessor: Vendor ID Register
- PCIE_LM_VIRTUAL_FUNCTION_BAR_CONFIGURATION_0 (rw) register accessor: Virtual Function BAR Configuration Register 0
- PCIE_LM_VIRTUAL_FUNCTION_BAR_CONFIGURATION_1 (rw) register accessor: Virtual Function BAR Configuration Register 1
- PCIE_PF_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL (rw) register accessor: Advanced Error Capabilities and Control Register
- PCIE_PF_ADVANCED_ERROR_REPORTING_AER_ENHANCED_CAPABILITY_HEADER (r) register accessor: Advanced Error Reporting (AER) Enhanced Capability Header Register
- PCIE_PF_ARI_CAPABILITY_AND_ARI_CONTROL (r) register accessor: ARI Capability Register and ARI Control Register
- PCIE_PF_ARI_EXTENDED_CAPABILITY_HEADER (r) register accessor: ARI Extended Capability Header Register
- PCIE_PF_BASE_ADDRESS_0 (rw) register accessor: Base Address Register 0
- PCIE_PF_BASE_ADDRESS_1 (rw) register accessor: Base Address Register 1
- PCIE_PF_BASE_ADDRESS_2 (rw) register accessor: Base Address Register 2
- PCIE_PF_BASE_ADDRESS_3 (rw) register accessor: Base Address Register 3
- PCIE_PF_BASE_ADDRESS_4 (rw) register accessor: Base Address Register 4
- PCIE_PF_BASE_ADDRESS_5 (rw) register accessor: Base Address Register 5
- PCIE_PF_BIST_HEADER_TYPE_LATENCY_TIMER_AND_CACHE_LINE_SIZE_S (rw) register accessor: BIST, Header Type, Latency Timer and Cache Line Size Registers
- PCIE_PF_CAPABILITIES_POINTER (r) register accessor: Capabilities Pointer
- PCIE_PF_COMMAND_AND_STATUS (rw) register accessor: Command and Status Register
- PCIE_PF_CORRECTABLE_ERROR_MASK (rw) register accessor: Correctable Error Mask Register
- PCIE_PF_CORRECTABLE_ERROR_STATUS (rw) register accessor: Correctable Error Status Register
- PCIE_PF_DPA_CAPABILITY (r) register accessor: DPA Capability Register
- PCIE_PF_DPA_CONTROL_AND_STATUS_S (rw) register accessor: DPA Control and Status Registers
- PCIE_PF_DPA_EXTENDED_CAPABILITY_HEADER (r) register accessor: DPA Extended Capability Header Register
- PCIE_PF_DPA_LATENCY_INDICATOR (r) register accessor: DPA Latency Indicator Register
- PCIE_PF_DYNAMIC_POWER_ALLOCATION_ARRAY_0 (r) register accessor: Dynamic Power Allocation Array Register 0
- PCIE_PF_DYNAMIC_POWER_ALLOCATION_ARRAY_1 (r) register accessor: Dynamic Power Allocation Array Register 1
- PCIE_PF_FUNCTION_DEPENDENCY_LINK_NUMVFS (rw) register accessor: Function Dependency Link/NumVFs Register
- PCIE_PF_HEADER_LOG_0 (r) register accessor: Header Log Register 0
- PCIE_PF_HEADER_LOG_1 (r) register accessor: Header Log Register 1
- PCIE_PF_HEADER_LOG_2 (r) register accessor: Header Log Register 2
- PCIE_PF_HEADER_LOG_3 (r) register accessor: Header Log Register 3
- PCIE_PF_INITIAL_VFS_TOTAL_VFS (r) register accessor: Initial VFs/Total VFs Register
- PCIE_PF_INTERRUPT_LINE_AND_INTERRUPT_PIN (rw) register accessor: Interrupt Line and Interrupt Pin Register
- PCIE_PF_L1_PM_SUBSTATES_CAPABILITIES (r) register accessor: L1 PM Substates Capabilities Register
- PCIE_PF_L1_PM_SUBSTATES_CONTROL_1 (rw) register accessor: L1 PM Substates Control 1 Register
- PCIE_PF_L1_PM_SUBSTATES_CONTROL_2 (rw) register accessor: L1 PM Substates Control 2 Register
- PCIE_PF_L1_PM_SUBSTATES_EXTENDED_CAPABILITY_HEADER (r) register accessor: L1 PM Substates Extended Capability Header Register
- PCIE_PF_LATENCY_TOLERANCE_REPORTING_LTR_EXTENDED_CAPABILITY_HEADER (r) register accessor: Latency Tolerance Reporting (LTR) Extended Capability Header Register
- PCIE_PF_LINK_CAPABILITIES (r) register accessor: Link Capabilities Register
- PCIE_PF_LINK_CAPABILITIES_2 (r) register accessor: Link Capabilities Register 2
- PCIE_PF_LINK_CONTROL_AND_STATUS (rw) register accessor: Link Control and Status Register
- PCIE_PF_LINK_CONTROL_AND_STATUS_2 (rw) register accessor: Link Control and Status Register 2
- PCIE_PF_LTR_MAX_SNOOP_MAX_NO_SNOOP_LATENCY (rw) register accessor: LTR Max Snoop/Max No-Snoop Latency Register
- PCIE_PF_MSI_CONTROL (rw) register accessor: MSI Control Register
- PCIE_PF_MSI_MASK (rw) register accessor: MSI Mask Register
- PCIE_PF_MSI_MESSAGE_DATA (rw) register accessor: MSI Message Data Register
- PCIE_PF_MSI_MESSAGE_HIGH_ADDRESS (rw) register accessor: MSI Message High Address Register
- PCIE_PF_MSI_MESSAGE_LOW_ADDRESS (rw) register accessor: MSI Message Low Address Register
- PCIE_PF_MSI_PENDING_BITS (r) register accessor: MSI Pending Bits Register
- PCIE_PF_MSI_X_CONTROL (rw) register accessor: MSI-X Control Register
- PCIE_PF_MSI_X_PENDING_INTERRUPT (r) register accessor: MSI-X Pending Interrupt Register
- PCIE_PF_MSI_X_TABLE_OFFSET (r) register accessor: MSI-X Table Offset Register
- PCIE_PF_PCI_EXPRESS_CAPABILITY_LIST (r) register accessor: PCI Express Capability List Register
- PCIE_PF_PCI_EXPRESS_DEVICE_CAPABILITIES (r) register accessor: PCI Express Device Capabilities Register
- PCIE_PF_PCI_EXPRESS_DEVICE_CAPABILITIES_2 (r) register accessor: PCI Express Device Capabilities Register 2
- PCIE_PF_PCI_EXPRESS_DEVICE_CONTROL_AND_STATUS (rw) register accessor: PCI Express Device Control and Status Register
- PCIE_PF_PCI_EXPRESS_DEVICE_CONTROL_AND_STATUS_2 (rw) register accessor: PCI Express Device Control and Status Register 2
- PCIE_PF_POWER_BUDGET_CAPABILITY (r) register accessor: Power Budget Capability Register
- PCIE_PF_POWER_BUDGETING_DATA (r) register accessor: Power Budgeting Data Register
- PCIE_PF_POWER_BUDGETING_DATA_SELECT (rw) register accessor: Power Budgeting Data Select Register
- PCIE_PF_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER (r) register accessor: Power Budgeting Enhanced Capability Header
- PCIE_PF_POWER_MANAGEMENT_CAPABILITIES (r) register accessor: Power Management Capabilities Register
- PCIE_PF_POWER_MANAGEMENT_CONTROL_STATUS_REPORT (rw) register accessor: Power Management Control/Status Report
- PCIE_PF_RESIZABLE_BAR_CAPABILITY_0 (r) register accessor: Resizable BAR Capability Register 0
- PCIE_PF_RESIZABLE_BAR_CAPABILITY_1 (r) register accessor: Resizable BAR Capability Register 1
- PCIE_PF_RESIZABLE_BAR_CAPABILITY_2 (r) register accessor: Resizable BAR Capability Register 2
- PCIE_PF_RESIZABLE_BAR_CAPABILITY_3 (r) register accessor: Resizable BAR Capability Register 3
- PCIE_PF_RESIZABLE_BAR_CAPABILITY_4 (r) register accessor: Resizable BAR Capability Register 4
- PCIE_PF_RESIZABLE_BAR_CAPABILITY_5 (r) register accessor: Resizable BAR Capability Register 5
- PCIE_PF_RESIZABLE_BAR_CONTROL_0 (r) register accessor: Resizable BAR Control Register 0
- PCIE_PF_RESIZABLE_BAR_CONTROL_1 (r) register accessor: Resizable BAR Control Register 1
- PCIE_PF_RESIZABLE_BAR_CONTROL_2 (r) register accessor: Resizable BAR Control Register 2
- PCIE_PF_RESIZABLE_BAR_CONTROL_3 (r) register accessor: Resizable BAR Control Register 3
- PCIE_PF_RESIZABLE_BAR_CONTROL_4 (r) register accessor: Resizable BAR Control Register 4
- PCIE_PF_RESIZABLE_BAR_CONTROL_5 (r) register accessor: Resizable BAR Control Register 5
- PCIE_PF_RESIZABLE_BAR_EXTENDED_CAPABILITY_HEADER (r) register accessor: Resizable BAR Extended Capability Header Register
- PCIE_PF_REVISION_ID_AND_CLASS_CODE (r) register accessor: Revision ID and Class Code Register
- PCIE_PF_SR_IOV_CAPABILITIES (r) register accessor: SR-IOV Capabilities Register
- PCIE_PF_SR_IOV_CONTROL_AND_STATUS_S (rw) register accessor: SR-IOV Control and Status Registers
- PCIE_PF_SR_IOV_EXTENDED_CAPABILITY_HEADER (r) register accessor: SR-IOV Extended Capability Header Register
- PCIE_PF_SUBSYSTEM_VENDOR_ID_AND_SUBSYSTEM_ID (r) register accessor: Subsystem Vendor ID and Subsystem ID Register
- PCIE_PF_SUPPORTED_PAGE_SIZES (r) register accessor: Supported Page Sizes Register
- PCIE_PF_SYSTEM_PAGE_SIZE (rw) register accessor: System Page Size Register
- PCIE_PF_TPH_REQUESTER_CAPABILITY (r) register accessor: TPH Requester Capability Register
- PCIE_PF_TPH_REQUESTER_CONTROL (rw) register accessor: TPH Requester Control Register
- PCIE_PF_TPH_REQUESTER_EXTENDED_CAPABILITY_HEADER (r) register accessor: TPH Requester Extended Capability Header Register
- PCIE_PF_TPH_ST_TABLE_0 (rw) register accessor: TPH ST Table 0
- PCIE_PF_TPH_ST_TABLE_1 (rw) register accessor: TPH ST Table 1
- PCIE_PF_TPH_ST_TABLE_2 (rw) register accessor: TPH ST Table 2
- PCIE_PF_TPH_ST_TABLE_3 (rw) register accessor: TPH ST Table 3
- PCIE_PF_UNCORRECTABLE_ERROR_MASK (rw) register accessor: Uncorrectable Error Mask Register
- PCIE_PF_UNCORRECTABLE_ERROR_SEVERITY (rw) register accessor: Uncorrectable Error Severity Register
- PCIE_PF_UNCORRECTABLE_ERROR_STATUS (rw) register accessor: Uncorrectable Error Status Register
- PCIE_PF_VENDOR_ID_AND_DEVICE_ID (r) register accessor: Vendor ID and Device ID
- PCIE_PF_VF_BASE_ADDRESS_0 (rw) register accessor: VF Base Address Register 0
- PCIE_PF_VF_BASE_ADDRESS_1 (rw) register accessor: VF Base Address Register 1
- PCIE_PF_VF_BASE_ADDRESS_2 (rw) register accessor: VF Base Address Register 2
- PCIE_PF_VF_BASE_ADDRESS_3 (rw) register accessor: VF Base Address Register 3
- PCIE_PF_VF_BASE_ADDRESS_4 (rw) register accessor: VF Base Address Register 4
- PCIE_PF_VF_BASE_ADDRESS_5 (rw) register accessor: VF Base Address Register 5
- PCIE_PF_VF_DEVICE_ID (r) register accessor: VF Device ID Register
- PCIE_PF_VF_MIGRATION_STATE_ARRAY_OFFSET (r) register accessor: VF Migration State Array Offset Register
- PCIE_PF_VF_OFFSET_STRIDE (r) register accessor: VF Offset/Stride Register
- PCIE_RC_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL (rw) register accessor: Advanced Error Capabilities and Control Register
- PCIE_RC_ADVANCED_ERROR_REPORTING_AER_ENHANCED_CAPABILITY_HEADER (r) register accessor: Advanced Error Reporting (AER) Enhanced Capability Header Register
- PCIE_RC_BIST_HEADER_TYPE_LATENCY_TIMER_AND_CACHE_LINE_SIZE_S (rw) register accessor: BIST, Header Type, Latency Timer and Cache Line Size Registers
- PCIE_RC_CAPABILITIES_POINTER (r) register accessor: Capabilities Pointer
- PCIE_RC_COMMAND_AND_STATUS (rw) register accessor: Command and Status Register
- PCIE_RC_CORRECTABLE_ERROR_MASK (rw) register accessor: Correctable Error Mask Register
- PCIE_RC_CORRECTABLE_ERROR_STATUS (rw) register accessor: Correctable Error Status Register
- PCIE_RC_ERROR_SOURCE_IDENTIFICATION (r) register accessor: Error Source Identification Register
- PCIE_RC_HEADER_LOG_0 (r) register accessor: Header Log Register 0
- PCIE_RC_HEADER_LOG_1 (r) register accessor: Header Log Register 1
- PCIE_RC_HEADER_LOG_2 (r) register accessor: Header Log Register 2
- PCIE_RC_HEADER_LOG_3 (r) register accessor: Header Log Register 3
- PCIE_RC_INTERRUPT_LINE_INTERRUPT_PIN_AND_BRIDGE_CONTROL (rw) register accessor: Interrupt Line, Interrupt Pin Register and Bridge Control Register
- PCIE_RC_IO_BASE_IO_LIMIT_SECONDARY_STATUS (rw) register accessor: IO Base, IO Limit, Secondary Status Register
- PCIE_RC_IO_BASE_UPPER_IO_LIMIT_UPPER (r) register accessor: IO Base Upper, IO Limit Upper
- PCIE_RC_L1_PM_SUBSTATES_CAPABILITIES (r) register accessor: L1 PM Substates Capabilities Register
- PCIE_RC_L1_PM_SUBSTATES_CONTROL_1 (rw) register accessor: L1 PM Substates Control 1 Register
- PCIE_RC_L1_PM_SUBSTATES_CONTROL_2 (rw) register accessor: L1 PM Substates Control 2 Register
- PCIE_RC_L1_PM_SUBSTATES_EXTENDED_CAPABILITY_HEADER (r) register accessor: L1 PM Substates Extended Capability Header Register
- PCIE_RC_LINK_CAPABILITIES (r) register accessor: Link Capabilities Register
- PCIE_RC_LINK_CAPABILITIES_2 (r) register accessor: Link Capabilities Register 2
- PCIE_RC_LINK_CONTROL_AND_STATUS (rw) register accessor: Link Control and Status Register
- PCIE_RC_LINK_CONTROL_AND_STATUS_2 (rw) register accessor: Link Control and Status 2 Register
- PCIE_RC_MEMORY_BASE_MEMORY_LIMIT (rw) register accessor: Memory Base, Memory Limit
- PCIE_RC_MSI_CONTROL (rw) register accessor: MSI Control Register
- PCIE_RC_MSI_MASK (rw) register accessor: MSI Mask Register
- PCIE_RC_MSI_MESSAGE_DATA (rw) register accessor: MSI Message Data Register
- PCIE_RC_MSI_MESSAGE_HIGH_ADDRESS (rw) register accessor: MSI Message High Address Register
- PCIE_RC_MSI_MESSAGE_LOW_ADDRESS (rw) register accessor: MSI Message Low Address Register
- PCIE_RC_MSI_PENDING_BITS (r) register accessor: MSI Pending Bits Register
- PCIE_RC_MSI_X_CONTROL (rw) register accessor: MSI-X Control Register
- PCIE_RC_MSI_X_PENDING_INTERRUPT (r) register accessor: MSI-X Pending Interrupt Register
- PCIE_RC_MSI_X_TABLE_OFFSET (r) register accessor: MSI-X Table Offset Register
- PCIE_RC_PCI_EXPRESS_CAPABILITY_LIST (r) register accessor: PCI Express Capability List Register
- PCIE_RC_PCI_EXPRESS_DEVICE_CAPABILITIES (r) register accessor: PCI Express Device Capabilities Register
- PCIE_RC_PCI_EXPRESS_DEVICE_CAPABILITIES_2 (r) register accessor: PCI Express Device Capabilities 2 Register
- PCIE_RC_PCI_EXPRESS_DEVICE_CONTROL_AND_STATUS (rw) register accessor: PCI Express Device Control and Status Register
- PCIE_RC_PCI_EXPRESS_DEVICE_CONTROL_AND_STATUS_2 (rw) register accessor: PCI Express Device Control and Status 2 Register
- PCIE_RC_POWER_MANAGEMENT_CAPABILITIES (r) register accessor: Power Management Capabilities Register
- PCIE_RC_POWER_MANAGEMENT_CONTROL_STATUS_REPORT (rw) register accessor: Power Management Control/Status Report
- PCIE_RC_PREFETCHABLE_BASE_UPPER (r) register accessor: Prefetchable Base Upper
- PCIE_RC_PREFETCHABLE_LIMIT_UPPER (r) register accessor: Prefetchable Limit Upper
- PCIE_RC_PREFETCHABLE_MEMORY_BASE_PREFETCHABLE_MEMORY_LIMIT (r) register accessor: Prefetchable Memory Base, Prefetchable Memory Limit
- PCIE_RC_PRIMARY_BUS_NUMBER_SECONDARY_BUS_NUMBER_SUBORDINATE_BUS_NUMBER_SECONDARY_LATENCY_TIMER (rw) register accessor: Primary Bus Number, Secondary Bus Number, Subordinate Bus Number, Secondary Latency Timer
- PCIE_RC_REVISION_ID_AND_CLASS_CODE (r) register accessor: Revision ID and Class Code Register
- PCIE_RC_ROOT_COMPLEX_BASE_ADDRESS_0 (rw) register accessor: Root Complex Base Address Register 0
- PCIE_RC_ROOT_COMPLEX_BASE_ADDRESS_1 (rw) register accessor: Root Complex Base Address Register 1
- PCIE_RC_ROOT_CONTROL_AND_CAPABILITY (rw) register accessor: Root Control and Capability Register
- PCIE_RC_ROOT_ERROR_COMMAND (rw) register accessor: Root Error Command Register
- PCIE_RC_ROOT_ERROR_STATUS (rw) register accessor: Root Error Status Register
- PCIE_RC_ROOT_STATUS (rw) register accessor: Root Status Register
- PCIE_RC_SLOT_CAPABILITY (rw) register accessor: Slot Capability Register
- PCIE_RC_SLOT_CONTROL_AND_STATUS (rw) register accessor: Slot Control and Status Register
- PCIE_RC_TPH_ST_TABLE_3 (rw) register accessor: TPH ST Table 3
- PCIE_RC_UNCORRECTABLE_ERROR_MASK (rw) register accessor: Uncorrectable Error Mask Register
- PCIE_RC_UNCORRECTABLE_ERROR_SEVERITY (rw) register accessor: Uncorrectable Error Severity Register
- PCIE_RC_UNCORRECTABLE_ERROR_STATUS (rw) register accessor: Uncorrectable Error Status Register
- PCIE_RC_VENDOR_ID_AND_DEVICE_ID (r) register accessor: Vendor ID and Device ID
- PCIE_VF_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL (r) register accessor: Advanced Error Capabilities and Control Register
- PCIE_VF_ADVANCED_ERROR_REPORTING_AER_ENHANCED_CAPABILITY_HEADER (r) register accessor: Advanced Error Reporting (AER) Enhanced Capability Header Register
- PCIE_VF_ARI_CAPABILITY_AND_ARI_CONTROL (r) register accessor: ARI Capability Register and ARI Control Register
- PCIE_VF_ARI_EXTENDED_CAPABILITY_HEADER (r) register accessor: ARI Extended Capability Header Register
- PCIE_VF_BASE_ADDRESS_0 (r) register accessor: Base Address Register 0
- PCIE_VF_BASE_ADDRESS_1 (r) register accessor: Base Address Register 1
- PCIE_VF_BASE_ADDRESS_2 (r) register accessor: Base Address Register 2
- PCIE_VF_BASE_ADDRESS_3 (r) register accessor: Base Address Register 3
- PCIE_VF_BASE_ADDRESS_4 (r) register accessor: Base Address Register 4
- PCIE_VF_BASE_ADDRESS_5 (r) register accessor: Base Address Register 5
- PCIE_VF_BIST_HEADER_TYPE_LATENCY_TIMER_AND_CACHE_LINE_SIZE_S (r) register accessor: BIST, Header Type, Latency Timer and Cache Line Size Registers
- PCIE_VF_CAPABILITIES_POINTER (r) register accessor: Capabilities Pointer
- PCIE_VF_COMMAND_AND_STATUS (rw) register accessor: Command and Status Register
- PCIE_VF_CORRECTABLE_ERROR_MASK (r) register accessor: Correctable Error Mask Register
- PCIE_VF_CORRECTABLE_ERROR_STATUS (rw) register accessor: Correctable Error Status Register
- PCIE_VF_EXPANSION_ROM_BASE_ADDRESS (r) register accessor: Expansion ROM Base Address Register
- PCIE_VF_HEADER_LOG_0 (r) register accessor: Header Log Register 0
- PCIE_VF_HEADER_LOG_1 (r) register accessor: Header Log Register 1
- PCIE_VF_HEADER_LOG_2 (r) register accessor: Header Log Register 2
- PCIE_VF_HEADER_LOG_3 (r) register accessor: Header Log Register 3
- PCIE_VF_INTERRUPT_LINE_AND_INTERRUPT_PIN (r) register accessor: Interrupt Line and Interrupt Pin Register
- PCIE_VF_LINK_CAPABILITIES (r) register accessor: Link Capabilities Register
- PCIE_VF_MSI_CONTROL (rw) register accessor: MSI Control Register
- PCIE_VF_MSI_MASK (rw) register accessor: MSI Mask Register
- PCIE_VF_MSI_MESSAGE_DATA (rw) register accessor: MSI Message Data Register
- PCIE_VF_MSI_MESSAGE_HIGH_ADDRESS (rw) register accessor: MSI Message High Address Register
- PCIE_VF_MSI_MESSAGE_LOW_ADDRESS (rw) register accessor: MSI Message Low Address Register
- PCIE_VF_MSI_PENDING_BITS (r) register accessor: MSI Pending Bits Register
- PCIE_VF_MSI_X_CONTROL (rw) register accessor: MSI-X Control Register
- PCIE_VF_MSI_X_PENDING_INTERRUPT (r) register accessor: MSI-X Pending Interrupt Register
- PCIE_VF_MSI_X_TABLE_OFFSET (r) register accessor: MSI-X Table Offset Register
- PCIE_VF_PCI_EXPRESS_CAPABILITY_LIST (r) register accessor: PCI Express Capability List Register
- PCIE_VF_PCI_EXPRESS_DEVICE_CAPABILITIES (r) register accessor: PCI Express Device Capabilities Register
- PCIE_VF_PCI_EXPRESS_DEVICE_CAPABILITIES_2 (r) register accessor: PCI Express Device Capabilities Register 2
- PCIE_VF_PCI_EXPRESS_DEVICE_CONTROL_AND_STATUS (rw) register accessor: PCI Express Device Control and Status Register
- PCIE_VF_POWER_MANAGEMENT_CAPABILITIES (r) register accessor: Power Management Capabilities Register
- PCIE_VF_POWER_MANAGEMENT_CONTROL_STATUS_REPORT (rw) register accessor: Power Management Control/Status Report
- PCIE_VF_REVISION_ID_AND_CLASS_CODE (r) register accessor: Revision ID and Class Code Register
- PCIE_VF_SUBSYSTEM_VENDOR_ID_AND_SUBSYSTEM_ID (r) register accessor: Subsystem Vendor ID and Subsystem ID Register
- PCIE_VF_TPH_REQUESTER_CAPABILITY (r) register accessor: TPH Requester Capability Register
- PCIE_VF_TPH_REQUESTER_CONTROL (rw) register accessor: TPH Requester Control Register
- PCIE_VF_TPH_REQUESTER_ENHANCED_CAPABILITY_HEADER (r) register accessor: TPH Requester Enhanced Capability Header Register
- PCIE_VF_TPH_ST_TABLE_0 (rw) register accessor: TPH ST Table 0
- PCIE_VF_TPH_ST_TABLE_1 (rw) register accessor: TPH ST Table 1
- PCIE_VF_TPH_ST_TABLE_2 (rw) register accessor: TPH ST Table 2
- PCIE_VF_UNCORRECTABLE_ERROR_MASK (r) register accessor: Uncorrectable Error Mask Register
- PCIE_VF_UNCORRECTABLE_ERROR_SEVERITY (r) register accessor: Uncorrectable Error Severity Register
- PCIE_VF_UNCORRECTABLE_ERROR_STATUS (rw) register accessor: Uncorrectable Error Status Register
- PCIE_VF_VENDOR_ID_AND_DEVICE_ID (r) register accessor: Vendor ID and Device ID