Module rk3399_pac::msch
source · Expand description
Memory Schedule (MSCH) Registers
Modules§
- Aging threshold multiplicator.
- ddr mode definition.
- DdrTimingA bank 0
- DdrTimingB bank 0
- DdrTimingC bank 0
- Timing values concerning device to device data bus ownership c
- ddr configuration pointers
- ddr configuration sizes.
- Core ID register
- Revision ID register
Structs§
- Register block
Type Aliases§
- AgingX0 (rw) register accessor: Aging threshold multiplicator.
- DdrMode (rw) register accessor: ddr mode definition.
- DdrTimingA0 (rw) register accessor: DdrTimingA bank 0
- DdrTimingB0 (rw) register accessor: DdrTimingB bank 0
- DdrTimingC0 (rw) register accessor: DdrTimingC bank 0
- DevToDev0 (rw) register accessor: Timing values concerning device to device data bus ownership c
- DeviceConf (rw) register accessor: ddr configuration pointers
- DeviceSize (rw) register accessor: ddr configuration sizes.
- Id_CoreId (r) register accessor: Core ID register
- Id_RevisionId (r) register accessor: Revision ID register