Module rk3399_pac::mipi_dsi_host
source · Expand description
MIPI Display Serial Interface (DSI) Host Registers
Modules§
- Peripheral Response Timeout Definition after B
- Internal Clock Dividers Configuration Register
- Command Mode Configuration Register
- Command Packet Status Register
- DPI Polarity Configuration Register
- DPI Color Coding Register
- Low-Power Command Timing Configuration Register
- DPI Virtual Channel ID Register
- eDPI Packet Size Register
- Generic Packet Header Configuration Register
- Generic Payload Data In And Out Register
- Generic Interface Virtual Channel Id Register
- Peripheral Response Timeout Definition after Hi
- Peripheral Response Timeout Definition after Hi
- Force Interrupt Configuration Register
- Force Interrupt Configuration Register
- Masks the Interrupt Generation Triggered by the
- Masks the Interrupt Generation Triggered by the
- Interrupt Status Register 0
- Interrupt Status Register 1
- Peripheral Response Timeout Definition after Lo
- Peripheral Response Timeout Definition after Lo
- Low-power in Clock Lane Register
- Register0000 Abstract
- Packet Handler Configuration Register
- D-PHY Interface Configuration Register
- D-PHY Reset Control Register
- Register0010 Abstract
- D-PHY Data Lanes Timing Configuration Registe
- D-PHY Timing Configuration for the Clock Lane
- D-PHY Test Interface Control 0 Register
- D-PHY Test Interface Control 1 Register
- D-PHY Transmit Triggers Register
- D-PHY Ultra Low-Power Control Register
- PWR_UP
- Timeout Timers Configuration Register
- VERSION
- Register0005 Abstract
- Line Time Register
- Horizontal Sync Active Time Register
- Video Mode Configuration Register
- Null Packet Size Register
- Number Of Chunks Register
- Video Packet Size Register
- Vertical Resolution Register
- Vertical Back Porch Period Register
- Vertical Front Porch Period Register
- VID_VSA_LINES
Structs§
- Register block
Type Aliases§
- BTA_TO_CNT (rw) register accessor: Peripheral Response Timeout Definition after B
- CLKMGR_CFG (rw) register accessor: Internal Clock Dividers Configuration Register
- CMD_MODE_CFG (rw) register accessor: Command Mode Configuration Register
- CMD_PKT_STATUS (r) register accessor: Command Packet Status Register
- DPI_CFG_POL (rw) register accessor: DPI Polarity Configuration Register
- DPI_COLOR_CODING (rw) register accessor: DPI Color Coding Register
- DPI_LP_CMD_TIM (rw) register accessor: Low-Power Command Timing Configuration Register
- DPI_VCID (rw) register accessor: DPI Virtual Channel ID Register
- EDPI_CMD_SIZE (rw) register accessor: eDPI Packet Size Register
- GEN_HDR (rw) register accessor: Generic Packet Header Configuration Register
- GEN_PLD_DATA (rw) register accessor: Generic Payload Data In And Out Register
- GEN_VCID (rw) register accessor: Generic Interface Virtual Channel Id Register
- HS_RD_TO_CNT (rw) register accessor: Peripheral Response Timeout Definition after Hi
- HS_WR_TO_CNT (rw) register accessor: Peripheral Response Timeout Definition after Hi
- INT_FORCE0 (w) register accessor: Force Interrupt Configuration Register
- INT_FORCE1 (w) register accessor: Force Interrupt Configuration Register
- INT_MSK0 (r) register accessor: Masks the Interrupt Generation Triggered by the
- INT_MSK1 (r) register accessor: Masks the Interrupt Generation Triggered by the
- INT_ST0 (r) register accessor: Interrupt Status Register 0
- INT_ST1 (r) register accessor: Interrupt Status Register 1
- LP_RD_TO_CNT (rw) register accessor: Peripheral Response Timeout Definition after Lo
- LP_WR_TO_CNT (rw) register accessor: Peripheral Response Timeout Definition after Lo
- LPCLK_CTRL (rw) register accessor: Low-power in Clock Lane Register
- MODE_CFG (rw) register accessor: Register0000 Abstract
- PCKHDL_CFG (rw) register accessor: Packet Handler Configuration Register
- PHY_IF_CFG (rw) register accessor: D-PHY Interface Configuration Register
- PHY_RSTZ (rw) register accessor: D-PHY Reset Control Register
- PHY_STATUS (r) register accessor: Register0010 Abstract
- PHY_TMR_CFG (rw) register accessor: D-PHY Data Lanes Timing Configuration Registe
- PHY_TMR_LPCLK_CFG (rw) register accessor: D-PHY Timing Configuration for the Clock Lane
- PHY_TST_CTRL0 (rw) register accessor: D-PHY Test Interface Control 0 Register
- PHY_TST_CTRL1 (rw) register accessor: D-PHY Test Interface Control 1 Register
- PHY_TX_TRIGGERS (rw) register accessor: D-PHY Transmit Triggers Register
- PHY_ULPS_CTRL (rw) register accessor: D-PHY Ultra Low-Power Control Register
- PWR_UP (rw) register accessor: PWR_UP
- TO_CNT_CFG (rw) register accessor: Timeout Timers Configuration Register
- VERSION (rw) register accessor: VERSION
- VID_HBP_TIME (rw) register accessor: Register0005 Abstract
- VID_HLINE_TIME (rw) register accessor: Line Time Register
- VID_HSA_TIME (rw) register accessor: Horizontal Sync Active Time Register
- VID_MODE_CFG (rw) register accessor: Video Mode Configuration Register
- VID_NULL_SIZE (rw) register accessor: Null Packet Size Register
- VID_NUM_CHUNKS (rw) register accessor: Number Of Chunks Register
- VID_PKT_SIZE (rw) register accessor: Video Packet Size Register
- VID_VACTIVE_LINES (rw) register accessor: Vertical Resolution Register
- VID_VBP_LINES (rw) register accessor: Vertical Back Porch Period Register
- VID_VFP_LINES (rw) register accessor: Vertical Front Porch Period Register
- VID_VSA_LINES (rw) register accessor: VID_VSA_LINES