Module rk3399_pac::hdmi

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HDMI Registers

Modules§

Structs§

Type Aliases§

  • AApiintclr
    A_APIINTCLR (w) register accessor: HDCP Interrupt Clear Register
  • AApiintmsk
    A_APIINTMSK (rw) register accessor: HDCP Interrupt Mask Register
  • AApiintstat
    A_APIINTSTAT (r) register accessor: HDCP Interrupt Status Register
  • ACoreverlsb
    A_COREVERLSB (r) register accessor: HDCP Controller Version Register LSB Design ID number.
  • ACorevermsb
    A_COREVERMSB (r) register accessor: HDCP Controller Version Register MSB Revision ID number.
  • AHdcpcfg0
    A_HDCPCFG0 (rw) register accessor: HDCP Enable and Functional Control Configuration Register 0
  • AHdcpcfg1
    A_HDCPCFG1 (rw) register accessor: HDCP Software Reset and Functional Control Configuration Register 1
  • AHdcpobs0
    A_HDCPOBS0 (r) register accessor: HDCP Observation Register 0
  • AHdcpobs1
    A_HDCPOBS1 (r) register accessor: HDCP Observation Register 1
  • AHdcpobs2
    A_HDCPOBS2 (r) register accessor: HDCP Observation Register 2
  • AHdcpobs3
    A_HDCPOBS3 (r) register accessor: HDCP Observation Register 3
  • AKsvmemctrl
    A_KSVMEMCTRL (rw) register accessor: HDCP KSV Memory Control Register
  • AOesswcfg
    A_OESSWCFG (rw) register accessor: HDCP OESS WOO Configuration Register
  • AVidpolcfg
    A_VIDPOLCFG (rw) register accessor: HDCP Video Polarity Configuration Register
  • AhbDmaBstraddr
    AHB_DMA_BSTRADDR (r) register accessor: Audio DMA Burst Start Address Register Array Address offset: i = 0 to 3
  • AhbDmaBuffmask
    AHB_DMA_BUFFMASK (rw) register accessor: Audio DMA Buffer Mask Interrupt Register
  • AhbDmaConf0
    AHB_DMA_CONF0 (rw) register accessor: Audio DMA SW FIFO reset and DMA Configuration Register 0
  • AhbDmaConf1
    AHB_DMA_CONF1 (rw) register accessor: Audio DMA Channel Enable Configuration Register 1
  • AhbDmaConf2
    AHB_DMA_CONF2 (rw) register accessor: Audio DMA Configuration Register 2
  • AhbDmaMask
    AHB_DMA_MASK (rw) register accessor: Audio DMA Mask Interrupt Register
  • AhbDmaMask1
    AHB_DMA_MASK1 (rw) register accessor: Audio DMA Mask Interrupt Register 1
  • AhbDmaMblength0
    AHB_DMA_MBLENGTH0 (r) register accessor: Audio DMA Burst Length Register 0
  • AhbDmaMblength1
    AHB_DMA_MBLENGTH1 (r) register accessor: Audio DMA Burst Length Register 1
  • AhbDmaStart
    AHB_DMA_START (rw) register accessor: Audio DMA Start Register
  • AhbDmaStatus
    AHB_DMA_STATUS (r) register accessor: Audio DMA Status
  • AhbDmaStop
    AHB_DMA_STOP (rw) register accessor: Audio DMA Stop Register
  • AhbDmaStpaddrSet0
    AHB_DMA_STPADDR_SET0 (rw) register accessor: Audio DMA Stop Address Set0 Register Array Address offset: i = 0 to 3
  • AhbDmaStpaddrSet1
    AHB_DMA_STPADDR_SET1 (rw) register accessor: Audio DMA Stop Address Set 1 Register Array Address offset: i = 0 to 3
  • AhbDmaStraddrSet0
    AHB_DMA_STRADDR_SET0 (rw) register accessor: Audio DMA Start Address Set0 Register Array Address offset: i = 0 to 3
  • AhbDmaStraddrSet1
    AHB_DMA_STRADDR_SET1 (rw) register accessor: Audio DMA Start Address Set 1 Register Array Address offset: i = 0 to 3
  • AhbDmaThrsld
    AHB_DMA_THRSLD (rw) register accessor: Audio DMA FIFO Threshold Register
  • AudConf0
    AUD_CONF0 (rw) register accessor: Audio I2S Software FIFO Reset, Select, and Enable Control Register 0
  • AudConf1
    AUD_CONF1 (rw) register accessor: Audio I2S Width Configuration Register 1 This register configures the data
  • AudConf2
    AUD_CONF2 (rw) register accessor: Audio I2S PCUV, NLPCM and HBR configuration Register 2
  • AudCts1
    AUD_CTS1 (rw) register accessor: Audio Clock Regenerator CTS Value Register 1 For CTS expected values, refer
  • AudCts2
    AUD_CTS2 (rw) register accessor: Audio Clock Regenerator CTS Register 2
  • AudCts3
    AUD_CTS3 (rw) register accessor: Audio Clock Regenerator CTS value Register 3. For CTS expected values, refer
  • AudCtsDither
    AUD_CTS_DITHER (rw) register accessor: Audio CTS Dither Register
  • AudInputclkfs
    AUD_INPUTCLKFS (rw) register accessor: Audio Input Clock FS Factor Register
  • AudInt
    AUD_INT (rw) register accessor: I2S FIFO status and interrupts.
  • AudN1
    AUD_N1 (rw) register accessor: Audio Clock Regenerator N Value Register 1 For N expected values, refer to
  • AudN2
    AUD_N2 (rw) register accessor: Audio Clock Regenerator N Value Register 2 For N expected values, refer to
  • AudN3
    AUD_N3 (rw) register accessor: Audio Clock Regenerator N Value Register 3 For N expected values, refer to
  • AudSpdif0
    AUD_SPDIF0 (rw) register accessor: Audio SPDIF Software FIFO Reset Control Register 0
  • AudSpdif1
    AUD_SPDIF1 (rw) register accessor: Audio SPDIF NLPCM and Width Configuration Register 1 This register
  • AudSpdif2
    AUD_SPDIF2 (rw) register accessor: Audio SPDIF Enable Confiiguration Register 2
  • AudSpdifint
    AUD_SPDIFINT (rw) register accessor: Audio SPDIF FIFO Empty/Full Mask Register
  • AudSpdifint1
    AUD_SPDIFINT1 (rw) register accessor: Audio SPDIF Mask Interrupt Register 1
  • BaseSfrdivhigh
    BASE_SFRDIVHIGH (rw) register accessor: SFR Clock Base Time Register High
  • BaseSfrdivlow
    BASE_SFRDIVLOW (rw) register accessor: SFR Clock Base Time Register Low
  • CecAddrH
    CEC_ADDR_H (rw) register accessor: CEC Logical Address Register High
  • CecAddrL
    CEC_ADDR_L (rw) register accessor: CEC Logical Address Register Low
  • CecCtrl
    CEC_CTRL (rw) register accessor: CEC Control Register
  • CecLock
    CEC_LOCK (rw) register accessor: CEC Buffer Lock Register
  • CecMask
    CEC_MASK (rw) register accessor: CEC Interrupt Mask Register
  • CecRxCnt
    CEC_RX_CNT (r) register accessor: CEC RX Frame Size Register
  • CecRxData
    CEC_RX_DATA (r) register accessor: CEC RX Data Register Array Address offset: i =0 to 15
  • CecTxCnt
    CEC_TX_CNT (rw) register accessor: CEC TX Frame Size Register
  • CecTxData
    CEC_TX_DATA (rw) register accessor: CEC TX Data Register Array Address offset: i = 0 to 15
  • CecWakeupctrl
    CEC_WAKEUPCTRL (rw) register accessor: CEC Wake-up Control Register
  • Config0Id
    CONFIG0_ID (r) register accessor: Configuration Identification Register 0
  • Config1Id
    CONFIG1_ID (r) register accessor: Configuration Identification Register 1
  • Config2Id
    CONFIG2_ID (r) register accessor: Configuration Identification Register 2
  • Config3Id
    CONFIG3_ID (r) register accessor: Configuration Identification Register 3
  • CscCfg
    CSC_CFG (rw) register accessor: Color Space Converter Interpolation and Decimation Configuration Register
  • CscCoefA1Lsb
    CSC_COEF_A1_LSB (rw) register accessor: Color Space Converter Matrix A1 Coefficient Register LSB Notes:
  • CscCoefA1Msb
    CSC_COEF_A1_MSB (rw) register accessor: Color Space Converter Matrix A1 Coefficient Register MSB Notes:
  • CscCoefA2Lsb
    CSC_COEF_A2_LSB (rw) register accessor: Color Space Converter Matrix A2 Coefficient Register LSB Color Space
  • CscCoefA2Msb
    CSC_COEF_A2_MSB (rw) register accessor: Color Space Converter Matrix A2 Coefficient Register MSB Color Space
  • CscCoefA3Lsb
    CSC_COEF_A3_LSB (rw) register accessor: Color Space Converter Matrix A3 Coefficient Register LSB Color Space
  • CscCoefA3Msb
    CSC_COEF_A3_MSB (rw) register accessor: Color Space Converter Matrix A3 Coefficient Register MSB Color Space
  • CscCoefA4Lsb
    CSC_COEF_A4_LSB (rw) register accessor: Color Space Converter Matrix A4 Coefficient Register LSB Color Space
  • CscCoefA4Msb
    CSC_COEF_A4_MSB (rw) register accessor: Color Space Converter Matrix A4 Coefficient Register MSB Color Space
  • CscCoefB1Lsb
    CSC_COEF_B1_LSB (rw) register accessor: Color Space Converter Matrix B1 Coefficient Register LSB Color Space
  • CscCoefB1Msb
    CSC_COEF_B1_MSB (rw) register accessor: Color Space Converter Matrix B1 Coefficient Register MSB Color Space
  • CscCoefB2Lsb
    CSC_COEF_B2_LSB (rw) register accessor: Color Space Converter Matrix B2 Coefficient Register LSB Color Space
  • CscCoefB2Msb
    CSC_COEF_B2_MSB (rw) register accessor: Color Space Converter Matrix B2 Coefficient Register MSB Color Space
  • CscCoefB3Lsb
    CSC_COEF_B3_LSB (rw) register accessor: Color Space Converter Matrix B3 Coefficient Register LSB Color Space
  • CscCoefB3Msb
    CSC_COEF_B3_MSB (rw) register accessor: Color Space Converter Matrix B3 Coefficient Register MSB Color Space
  • CscCoefB4Lsb
    CSC_COEF_B4_LSB (rw) register accessor: Color Space Converter Matrix B4 Coefficient Register LSB Color Space
  • CscCoefB4Msb
    CSC_COEF_B4_MSB (rw) register accessor: Color Space Converter Matrix B4 Coefficient Register MSB Color Space
  • CscCoefC1Lsb
    CSC_COEF_C1_LSB (rw) register accessor: Color Space Converter Matrix C1 Coefficient Register LSB Color Space
  • CscCoefC1Msb
    CSC_COEF_C1_MSB (rw) register accessor: Color Space Converter Matrix C1 Coefficient Register MSB Color Space
  • CscCoefC2Lsb
    CSC_COEF_C2_LSB (rw) register accessor: Color Space Converter Matrix C2 Coefficient Register LSB Color Space
  • CscCoefC2Msb
    CSC_COEF_C2_MSB (rw) register accessor: Color Space Converter Matrix C2 Coefficient Register MSB Color Space
  • CscCoefC3Lsb
    CSC_COEF_C3_LSB (rw) register accessor: Color Space Converter Matrix C3 Coefficient Register LSB Color Space
  • CscCoefC3Msb
    CSC_COEF_C3_MSB (rw) register accessor: Color Space Converter Matrix C3 Coefficient Register MSB Color Space
  • CscCoefC4Lsb
    CSC_COEF_C4_LSB (rw) register accessor: Color Space Converter Matrix C4 Coefficient Register LSB Color Space
  • CscCoefC4Msb
    CSC_COEF_C4_MSB (rw) register accessor: Color Space Converter Matrix C4 Coefficient Register MSB Color Space
  • CscLimitDnLsb
    CSC_LIMIT_DN_LSB (rw) register accessor: Color Space Converter Matrix output Down Limit Register LSB
  • CscLimitDnMsb
    CSC_LIMIT_DN_MSB (rw) register accessor: Color Space Converter Matrix output Down Limit Register MSB
  • CscLimitUpLsb
    CSC_LIMIT_UP_LSB (rw) register accessor: Color Space Converter Matrix output Up Limit Register LSB
  • CscLimitUpMsb
    CSC_LIMIT_UP_MSB (rw) register accessor: Color Space Converter Matrix Output Up Limit Register MSB
  • CscScale
    CSC_SCALE (rw) register accessor: Color Space Converter Scale and Deep Color Configuration Register
  • DesignId
    DESIGN_ID (r) register accessor: Design Identification Register
  • FcAcp0
    FC_ACP0 (rw) register accessor: Frame Composer ACP Packet Type Configuration Register 0
  • FcAcp1
    FC_ACP1 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 1
  • FcAcp2
    FC_ACP2 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 2
  • FcAcp3
    FC_ACP3 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 3
  • FcAcp4
    FC_ACP4 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 4
  • FcAcp5
    FC_ACP5 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 5
  • FcAcp6
    FC_ACP6 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 6
  • FcAcp7
    FC_ACP7 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 7
  • FcAcp8
    FC_ACP8 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 8
  • FcAcp9
    FC_ACP9 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 9
  • FcAcp10
    FC_ACP10 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 10
  • FcAcp11
    FC_ACP11 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 11
  • FcAcp12
    FC_ACP12 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 12
  • FcAcp13
    FC_ACP13 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 13
  • FcAcp14
    FC_ACP14 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 14
  • FcAcp15
    FC_ACP15 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 15
  • FcAcp16
    FC_ACP16 (rw) register accessor: Frame Composer ACP Packet Body Configuration Register 16
  • FcActspcHdlrCfg
    FC_ACTSPC_HDLR_CFG (rw) register accessor: Frame Composer Active Space Control
  • FcAmpHb1
    FC_AMP_HB1 (rw) register accessor: Frame Composer AMP Packet Header Register 1
  • FcAmpHb2
    FC_AMP_HB2 (rw) register accessor: Frame Composer AMP Packet Header Register 2
  • FcAmpPb
    FC_AMP_PB (rw) register accessor: Frame Composer AMP Packet Body Register Array
  • FcAudiconf0
    FC_AUDICONF0 (rw) register accessor: Frame Composer AUD Packet Configuration Register 0
  • FcAudiconf1
    FC_AUDICONF1 (rw) register accessor: Frame Composer AUD Packet Configuration Register 1
  • FcAudiconf2
    FC_AUDICONF2 (rw) register accessor: Frame Composer AUD Packet Configuration Register 2
  • FcAudiconf3
    FC_AUDICONF3 (rw) register accessor: Frame Composer AUD Packet Configuration Register 3
  • FcAudschnl0
    FC_AUDSCHNL0 (rw) register accessor: Frame Composer Audio Sample Channel Status Configuration Register 0
  • FcAudschnl1
    FC_AUDSCHNL1 (rw) register accessor: Frame Composer Audio Sample Channel Status Configuration Register 1
  • FcAudschnl2
    FC_AUDSCHNL2 (rw) register accessor: Frame Composer Audio Sample Channel Status Configuration Register 2
  • FcAudschnl3
    FC_AUDSCHNL3 (rw) register accessor: Frame Composer Audio Sample Channel Status Configuration Register 3
  • FcAudschnl4
    FC_AUDSCHNL4 (rw) register accessor: Frame Composer Audio Sample Channel Status Configuration Register 4
  • FcAudschnl5
    FC_AUDSCHNL5 (rw) register accessor: Frame Composer Audio Sample Channel Status Configuration Register 5
  • FcAudschnl6
    FC_AUDSCHNL6 (rw) register accessor: Frame Composer Audio Sample Channel Status Configuration Register 6
  • FcAudschnl7
    FC_AUDSCHNL7 (rw) register accessor: Frame Composer Audio Sample Channel Status Configuration Register 7
  • FcAudschnl8
    FC_AUDSCHNL8 (rw) register accessor: Frame Composer Audio Sample Channel Status Configuration Register 8
  • FcAudsconf
    FC_AUDSCONF (rw) register accessor: Frame Composer Audio Sample Flat and Layout Configuration Register
  • FcAudsstat
    FC_AUDSSTAT (r) register accessor: Frame Composer Audio Sample Flat and Layout Status Register
  • FcAudsu
    FC_AUDSU (rw) register accessor: Frame Composer Audio Sample User Flag Register
  • FcAudsv
    FC_AUDSV (rw) register accessor: Frame Composer Audio Sample Validity Flag Register
  • FcAviconf0
    FC_AVICONF0 (rw) register accessor: Frame Composer AVI Packet Configuration Register 0
  • FcAviconf1
    FC_AVICONF1 (rw) register accessor: Frame Composer AVI Packet Configuration Register 1
  • FcAviconf2
    FC_AVICONF2 (rw) register accessor: Frame Composer AVI Packet Configuration Register 2
  • FcAviconf3
    FC_AVICONF3 (rw) register accessor: Frame Composer AVI Packet Configuration Register 3
  • FcAvielb
    FC_AVIELB (rw) register accessor: Frame Composer AVI Packet End of Left Bar Register Array
  • FcAvietb
    FC_AVIETB (rw) register accessor: Frame Composer AVI Packet End of Top Bar Register Array
  • FcAvisbb
    FC_AVISBB (rw) register accessor: Frame Composer AVI Packet Start of Bottom Bar Register Array
  • FcAvisrb
    FC_AVISRB (rw) register accessor: Frame Composer AVI Packet Start of Right Bar Register Array
  • FcAvivid
    FC_AVIVID (rw) register accessor: Frame Composer AVI Packet VIC Register
  • FcCh0pream
    FC_CH0PREAM (rw) register accessor: Frame Composer Channel 0 Non-Preamble Data Register
  • FcCh1pream
    FC_CH1PREAM (rw) register accessor: Frame Composer Channel 1 Non-Preamble Data Register
  • FcCh2pream
    FC_CH2PREAM (rw) register accessor: Frame Composer Channel 2 Non-Preamble Data Register
  • FcCtrldur
    FC_CTRLDUR (rw) register accessor: Frame Composer Control Period Duration Register
  • FcCtrlqhigh
    FC_CTRLQHIGH (rw) register accessor: Frame Composer Number of High Priority Packets Attended Configuration
  • FcCtrlqlow
    FC_CTRLQLOW (rw) register accessor: Frame Composer Number of Low Priority Packets Attended Configuration
  • FcDatauto0
    FC_DATAUTO0 (rw) register accessor: Frame Composer Data Island Auto Packet Scheduling Register 0
  • FcDatauto1
    FC_DATAUTO1 (rw) register accessor: Frame Composer Data Island Auto Packet Scheduling Register 1
  • FcDatauto2
    FC_DATAUTO2 (rw) register accessor: Frame Composer Data Island Auto packet scheduling Register 2
  • FcDatauto3
    FC_DATAUTO3 (rw) register accessor: Frame Composer Data Island Auto Packet Scheduling Register 3
  • FcDatman
    FC_DATMAN (w) register accessor: Frame Composer Data Island Manual Packet Request Register
  • FcDbgaud0ch0
    FC_DBGAUD0CH0 (rw) register accessor: Frame Composer Audio Data Channel 0 Register 0
  • FcDbgaud0ch1
    FC_DBGAUD0CH1 (rw) register accessor: Frame Composer Audio Data Channel 1 Register 0
  • FcDbgaud0ch2
    FC_DBGAUD0CH2 (rw) register accessor: Frame Composer Audio Data Channel 2 Register 0
  • FcDbgaud0ch3
    FC_DBGAUD0CH3 (rw) register accessor: Frame Composer Audio Data Channel 3 Register 0
  • FcDbgaud0ch4
    FC_DBGAUD0CH4 (rw) register accessor: Frame Composer Audio Data Channel 4 Register 0
  • FcDbgaud0ch5
    FC_DBGAUD0CH5 (rw) register accessor: Frame Composer Audio Data Channel 5 Register 0
  • FcDbgaud0ch6
    FC_DBGAUD0CH6 (rw) register accessor: Frame Composer Audio Data Channel 6 Register 0
  • FcDbgaud0ch7
    FC_DBGAUD0CH7 (rw) register accessor: Frame Composer Audio Data Channel 7 Register 0
  • FcDbgaud1ch0
    FC_DBGAUD1CH0 (rw) register accessor: Frame Composer Audio Data Channel 0 Register 1
  • FcDbgaud1ch1
    FC_DBGAUD1CH1 (rw) register accessor: Frame Composer Audio Data Channel 1 Register 1
  • FcDbgaud1ch2
    FC_DBGAUD1CH2 (rw) register accessor: Frame Composer Audio Data Channel 2 Register 1
  • FcDbgaud1ch3
    FC_DBGAUD1CH3 (rw) register accessor: Frame Composer Audio Data Channel 3 Register 1
  • FcDbgaud1ch4
    FC_DBGAUD1CH4 (rw) register accessor: Frame Composer Audio Data Channel 4 Register 1
  • FcDbgaud1ch5
    FC_DBGAUD1CH5 (rw) register accessor: Frame Composer Audio Data Channel 5 Register 1
  • FcDbgaud1ch6
    FC_DBGAUD1CH6 (rw) register accessor: Frame Composer Audio Data Channel 6 Register 1
  • FcDbgaud1ch7
    FC_DBGAUD1CH7 (rw) register accessor: Frame Composer Audio Data Channel 7 Register 1
  • FcDbgaud2ch0
    FC_DBGAUD2CH0 (rw) register accessor: Frame Composer Audio Data Channel 0 Register 2
  • FcDbgaud2ch1
    FC_DBGAUD2CH1 (rw) register accessor: Frame Composer Audio Data Channel 1 Register 2
  • FcDbgaud2ch2
    FC_DBGAUD2CH2 (rw) register accessor: Frame Composer Audio Data Channel 2 Register 2
  • FcDbgaud2ch3
    FC_DBGAUD2CH3 (rw) register accessor: Frame Composer Audio Data Channel 3 Register 2
  • FcDbgaud2ch4
    FC_DBGAUD2CH4 (rw) register accessor: Frame Composer Audio Data Channel 4 Register 2
  • FcDbgaud2ch5
    FC_DBGAUD2CH5 (rw) register accessor: Frame Composer Audio Data Channel 5 Register 2
  • FcDbgaud2ch6
    FC_DBGAUD2CH6 (rw) register accessor: Frame Composer Audio Data Channel 6 Register 2
  • FcDbgaud2ch7
    FC_DBGAUD2CH7 (rw) register accessor: Frame Composer Audio Data Channel 7 Register 2
  • FcDbgforce
    FC_DBGFORCE (rw) register accessor: Frame Composer video/audio Force Enable Register
  • FcDbgtmds
    FC_DBGTMDS (rw) register accessor: Frame Composer TMDS Data Channel Register Array
  • FcDrmHb
    FC_DRM_HB (rw) register accessor: Frame Composer DRM Packet Header Register Array
  • FcDrmPb
    FC_DRM_PB (rw) register accessor: Frame Composer DRM Packet Body Register Array
  • FcDrmUp
    FC_DRM_UP (w) register accessor: Frame Composer DRM Packet Update Register
  • FcExctrldur
    FC_EXCTRLDUR (rw) register accessor: Frame Composer Extended Control Period Duration Register
  • FcExctrlspac
    FC_EXCTRLSPAC (rw) register accessor: Frame Composer Extended Control Period Maximum Spacing Register
  • FcGcp
    FC_GCP (rw) register accessor: Frame Composer GCP Packet Configuration Register
  • FcGmdConf
    FC_GMD_CONF (rw) register accessor: Frame Composer GMD Packet Schedule Configuration Register
  • FcGmdEn
    FC_GMD_EN (rw) register accessor: Frame Composer GMD Packet Enable Register
  • FcGmdHb
    FC_GMD_HB (rw) register accessor: Frame Composer GMD Packet Profile and Gamut Sequence Configuration
  • FcGmdPb
    FC_GMD_PB (rw) register accessor: Frame Composer GMD Packet Body Register Array Configures the GMD packet
  • FcGmdStat
    FC_GMD_STAT (r) register accessor: Frame Composer GMD Packet Status Register
  • FcGmdUp
    FC_GMD_UP (w) register accessor: Frame Composer GMD Packet Update Register
  • FcHsyncindelay0
    FC_HSYNCINDELAY0 (rw) register accessor: Frame Composer Input Video HSync Front Porch Register 0
  • FcHsyncindelay1
    FC_HSYNCINDELAY1 (rw) register accessor: Frame Composer Input Video HSync Front Porch Register 1
  • FcHsyncinwidth0
    FC_HSYNCINWIDTH0 (rw) register accessor: Frame Composer Input Video HSync Width Register 0
  • FcHsyncinwidth1
    FC_HSYNCINWIDTH1 (rw) register accessor: Frame Composer Input Video HSync Width Register 1
  • FcInfreq0
    FC_INFREQ0 (rw) register accessor: Frame Composer Input Video Refresh Rate Register 0
  • FcInfreq1
    FC_INFREQ1 (rw) register accessor: Frame Composer Input Video Refresh Rate Register 1
  • FcInfreq2
    FC_INFREQ2 (rw) register accessor: Frame Composer Input Video Refresh Rate Register 2
  • FcInhactiv0
    FC_INHACTIV0 (rw) register accessor: Frame Composer Input Video HActive Pixels Register 0
  • FcInhactiv1
    FC_INHACTIV1 (rw) register accessor: Frame Composer Input Video HActive Pixels Register 1
  • FcInhblank0
    FC_INHBLANK0 (rw) register accessor: Frame Composer Input Video HBlank Pixels Register 0
  • FcInhblank1
    FC_INHBLANK1 (rw) register accessor: Frame Composer Input Video HBlank Pixels Register 1
  • FcInvact2d0
    FC_INVACT_2D_0 (rw) register accessor: Frame Composer Input Video 2D VActive Pixels Register 0
  • FcInvact2d1
    FC_INVACT_2D_1 (rw) register accessor: Frame Composer Input Video VActive pixels Register 1
  • FcInvactiv0
    FC_INVACTIV0 (rw) register accessor: Frame Composer Input Video VActive Pixels Register 0
  • FcInvactiv1
    FC_INVACTIV1 (rw) register accessor: Frame Composer Input Video VActive Pixels Register 1
  • FcInvblank
    FC_INVBLANK (rw) register accessor: Frame Composer Input Video VBlank Pixels Register
  • FcInvidconf
    FC_INVIDCONF (rw) register accessor: Frame Composer Input Video Configuration and HDCP Keepout Register
  • FcIscr1_0
    FC_ISCR1_0 (rw) register accessor: Frame Composer ISRC1 Packet Status, Valid, and Continue Configuration
  • FcIscr1_1
    FC_ISCR1_1 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 1
  • FcIscr1_2
    FC_ISCR1_2 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 2
  • FcIscr1_3
    FC_ISCR1_3 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 3
  • FcIscr1_4
    FC_ISCR1_4 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 4
  • FcIscr1_5
    FC_ISCR1_5 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 5
  • FcIscr1_6
    FC_ISCR1_6 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 6
  • FcIscr1_7
    FC_ISCR1_7 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 7
  • FcIscr1_8
    FC_ISCR1_8 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 8
  • FcIscr1_9
    FC_ISCR1_9 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 9
  • FcIscr1_10
    FC_ISCR1_10 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 10
  • FcIscr1_11
    FC_ISCR1_11 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 11
  • FcIscr1_12
    FC_ISCR1_12 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 12
  • FcIscr1_13
    FC_ISCR1_13 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 13
  • FcIscr1_14
    FC_ISCR1_14 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 14
  • FcIscr1_15
    FC_ISCR1_15 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 15
  • FcIscr1_16
    FC_ISCR1_16 (rw) register accessor: Frame Composer ISRC1 Packet Body Register 16
  • FcIscr2_0
    FC_ISCR2_0 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 0
  • FcIscr2_1
    FC_ISCR2_1 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 1
  • FcIscr2_2
    FC_ISCR2_2 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 2
  • FcIscr2_3
    FC_ISCR2_3 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 3
  • FcIscr2_4
    FC_ISCR2_4 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 4
  • FcIscr2_5
    FC_ISCR2_5 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 5
  • FcIscr2_6
    FC_ISCR2_6 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 6
  • FcIscr2_7
    FC_ISCR2_7 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 7
  • FcIscr2_8
    FC_ISCR2_8 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 8
  • FcIscr2_9
    FC_ISCR2_9 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 9
  • FcIscr2_10
    FC_ISCR2_10 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 10
  • FcIscr2_11
    FC_ISCR2_11 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 11
  • FcIscr2_12
    FC_ISCR2_12 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 12
  • FcIscr2_13
    FC_ISCR2_13 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 13
  • FcIscr2_14
    FC_ISCR2_14 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 14
  • FcIscr2_15
    FC_ISCR2_15 (rw) register accessor: Frame Composer ISRC2 Packet Body Register 15
  • FcMask0
    FC_MASK0 (rw) register accessor: Frame Composer Packet Interrupt Mask Register 0
  • FcMask1
    FC_MASK1 (rw) register accessor: Frame Composer Packet Interrupt Mask Register 1
  • FcMask2
    FC_MASK2 (rw) register accessor: Frame Composer High/Low Priority Overflow and DRM Interrupt Mask Register
  • FcMultistreamCtrl
    FC_MULTISTREAM_CTRL (rw) register accessor: Frame Composer Multi-Stream Audio Control
  • FcNvbiHb1
    FC_NVBI_HB1 (rw) register accessor: Frame Composer NTSC VBI Packet Header Register 1
  • FcNvbiHb2
    FC_NVBI_HB2 (rw) register accessor: Frame Composer NTSC VBI Packet Header Register 2
  • FcNvbiPb
    FC_NVBI_PB (rw) register accessor: Frame Composer NTSC VBI Packet Body Register Array
  • FcPacketTxEn
    FC_PACKET_TX_EN (rw) register accessor: Frame Composer Packet Transmission Control
  • FcPrconf
    FC_PRCONF (rw) register accessor: Frame Composer Pixel Repetition Configuration Register
  • FcRdrb0
    FC_RDRB0 (rw) register accessor: Frame Composer Round Robin ACR Packet Insertion Register 0
  • FcRdrb1
    FC_RDRB1 (rw) register accessor: Frame Composer Round Robin ACR Packet Insertion Register 1
  • FcRdrb2
    FC_RDRB2 (rw) register accessor: Frame Composer Round Robin AUDI Packet Insertion Register 2
  • FcRdrb3
    FC_RDRB3 (rw) register accessor: Frame Composer Round Robin AUDI Packet Insertion Register 3
  • FcRdrb4
    FC_RDRB4 (rw) register accessor: Frame Composer Round Robin GCP Packet Insertion Register 4
  • FcRdrb5
    FC_RDRB5 (rw) register accessor: Frame Composer Round Robin GCP Packet Insertion Register 5
  • FcRdrb6
    FC_RDRB6 (rw) register accessor: Frame Composer Round Robin AVI Packet Insertion Register 6
  • FcRdrb7
    FC_RDRB7 (rw) register accessor: Frame Composer Round Robin AVI Packet Insertion Register 7
  • FcRdrb8
    FC_RDRB8 (rw) register accessor: Frame Composer Round Robin AMP Packet Insertion Register 8
  • FcRdrb9
    FC_RDRB9 (rw) register accessor: Frame Composer Round Robin AMP Packet Insertion Register 9
  • FcRdrb10
    FC_RDRB10 (rw) register accessor: Frame Composer Round Robin NTSC VBI Packet Insertion Register 10
  • FcRdrb11
    FC_RDRB11 (rw) register accessor: Frame Composer Round Robin NTSC VBI Packet Insertion Register 11
  • FcRdrb12
    FC_RDRB12 (rw) register accessor: Frame Composer Round Robin DRM Packet Insertion Register 12
  • FcRdrb13
    FC_RDRB13 (rw) register accessor: Frame Composer Round Robin DRM Packet Insertion Register 13
  • FcScramblerCtrl
    FC_SCRAMBLER_CTRL (rw) register accessor: Frame Composer Scrambler Control
  • FcSpddeviceinf
    FC_SPDDEVICEINF (rw) register accessor: Frame Composer SPD Packet Data Source Product Descriptor Register
  • FcSpdproductname
    FC_SPDPRODUCTNAME (rw) register accessor: Frame Composer SPD packet Data Product Name Register Array
  • FcSpdvendorname
    FC_SPDVENDORNAME (rw) register accessor: Frame Composer SPD Packet Data Vendor Name Register Array
  • FcVsdieeeid0
    FC_VSDIEEEID0 (rw) register accessor: Frame Composer VSI Packet Data IEEE Register 0
  • FcVsdieeeid1
    FC_VSDIEEEID1 (rw) register accessor: Frame Composer VSI Packet Data IEEE Register 1
  • FcVsdieeeid2
    FC_VSDIEEEID2 (rw) register accessor: Frame Composer VSI Packet Data IEEE Register 2
  • FcVsdpayload
    FC_VSDPAYLOAD (rw) register accessor: Frame Composer VSI Packet Data Payload Register Array
  • FcVsdsize
    FC_VSDSIZE (rw) register accessor: Frame Composer VSI Packet Data Size Register
  • FcVsyncindelay
    FC_VSYNCINDELAY (rw) register accessor: Frame Composer Input Video VSync Front Porch Register
  • FcVsyncinwidth
    FC_VSYNCINWIDTH (rw) register accessor: Frame Composer Input Video VSync Width Register
  • GpConf0
    GP_CONF0 (rw) register accessor: Audio GPA Software FIFO Reset Control Register 0
  • GpConf1
    GP_CONF1 (rw) register accessor: Audio GPA Channel Enable Configuration Register 1
  • GpConf2
    GP_CONF2 (rw) register accessor: Audio GPA HBR Enable Register 2
  • GpMask
    GP_MASK (rw) register accessor: Audio GPA FIFO Full and Empty Mask Interrupt Register
  • Hdcp22regCtrl
    HDCP22REG_CTRL (rw) register accessor: HDCP 2.2 Control Register
  • Hdcp22regCtrl1
    HDCP22REG_CTRL1 (rw) register accessor: HDCP 2.2 Control Register 1
  • Hdcp22regId
    HDCP22REG_ID (r) register accessor: HDCP 2.2 Identification Register
  • Hdcp22regMask
    HDCP22REG_MASK (rw) register accessor: HDCP 2.2 Interrupt Mask Register
  • Hdcp22regMute
    HDCP22REG_MUTE (rw) register accessor: HDCP 2.2 Interrupt Mute Vector
  • Hdcp22regStat
    HDCP22REG_STAT (rw) register accessor: HDCP 2.2 interrupt Sticky Bit Status Register
  • Hdcp22regSts
    HDCP22REG_STS (r) register accessor: HDCP 2.2 Status Register
  • HdcpBstatus
    HDCP_BSTATUS (rw) register accessor: HDCP BStatus Register Array
  • HdcpKsv
    HDCP_KSV (rw) register accessor: HDCP KSV Registers.
  • HdcpM0
    HDCP_M0 (rw) register accessor: HDCP M0 Register Array
  • HdcpRevocList
    HDCP_REVOC_LIST (rw) register accessor: HDCP Revocation KSV Registers.
  • HdcpRevocSize0
    HDCP_REVOC_SIZE_0 (rw) register accessor: HDCP Revocation KSV List Size Register 0
  • HdcpRevocSize1
    HDCP_REVOC_SIZE_1 (rw) register accessor: HDCP Revocation KSV List Size Register 1
  • HdcpVh
    HDCP_VH (rw) register accessor: HDCP SHA-1 VH Registers.
  • HdcpregAn0
    HDCPREG_AN0 (rw) register accessor: HDCP Forced AN Register 0
  • HdcpregAn1
    HDCPREG_AN1 (rw) register accessor: HDCP Forced AN Register 1
  • HdcpregAn2
    HDCPREG_AN2 (rw) register accessor: HDCP forced AN Register 2
  • HdcpregAn3
    HDCPREG_AN3 (rw) register accessor: HDCP Forced AN Register 3
  • HdcpregAn4
    HDCPREG_AN4 (rw) register accessor: HDCP Forced AN Register 4
  • HdcpregAn5
    HDCPREG_AN5 (rw) register accessor: HDCP Forced AN Register 5
  • HdcpregAn6
    HDCPREG_AN6 (rw) register accessor: HDCP Forced AN Register 6
  • HdcpregAn7
    HDCPREG_AN7 (rw) register accessor: HDCP Forced AN Register 7
  • HdcpregAnconf
    HDCPREG_ANCONF (rw) register accessor: HDCP AN Bypass Control Register
  • HdcpregBksv0
    HDCPREG_BKSV0 (r) register accessor: HDCP KSV Status Register 0
  • HdcpregBksv1
    HDCPREG_BKSV1 (r) register accessor: HDCP KSV Status Register 1
  • HdcpregBksv2
    HDCPREG_BKSV2 (r) register accessor: HDCP KSV Status Register 2
  • HdcpregBksv3
    HDCPREG_BKSV3 (r) register accessor: HDCP KSV Status Register 3
  • HdcpregBksv4
    HDCPREG_BKSV4 (r) register accessor: HDCP KSV Status Register 4
  • HdcpregDpk0
    HDCPREG_DPK0 (w) register accessor: HDCP Encrypted DPK Data Register 0
  • HdcpregDpk1
    HDCPREG_DPK1 (w) register accessor: HDCP Encrypted DPK Data Register 1
  • HdcpregDpk2
    HDCPREG_DPK2 (w) register accessor: HDCP Encrypted DPK Data Register 2
  • HdcpregDpk3
    HDCPREG_DPK3 (w) register accessor: HDCP Encrypted DPK Data Register 3
  • HdcpregDpk4
    HDCPREG_DPK4 (w) register accessor: HDCP Encrypted DPK Data Register 4
  • HdcpregDpk5
    HDCPREG_DPK5 (w) register accessor: HDCP Encrypted DPK Data Register 5
  • HdcpregDpk6
    HDCPREG_DPK6 (w) register accessor: HDCP Encrypted DPK Data Register 6
  • HdcpregRmlctl
    HDCPREG_RMLCTL (rw) register accessor: HDCP Encrypted Device Private Keys Control Register
  • HdcpregRmlsts
    HDCPREG_RMLSTS (r) register accessor: HDCP Encrypted DPK Status Register
  • HdcpregSeed0
    HDCPREG_SEED0 (w) register accessor: HDCP Encrypted DPK Seed Register 0
  • HdcpregSeed1
    HDCPREG_SEED1 (w) register accessor: HDCP Encrypted DPK Seed Register 1
  • I2cmAddress
    I2CM_ADDRESS (rw) register accessor: I2C DDC Address Configuration Register
  • I2cmCtlint
    I2CM_CTLINT (rw) register accessor: I2C DDC error Interrupt Register
  • I2cmDatai
    I2CM_DATAI (r) register accessor: I2C DDC Data read Register
  • I2cmDatao
    I2CM_DATAO (rw) register accessor: I2C DDC Data Write Register
  • I2cmDiv
    I2CM_DIV (rw) register accessor: I2C DDC Speed Control Register
  • I2cmFsSclHcnt0Addr
    I2CM_FS_SCL_HCNT_0_ADDR (rw) register accessor: I2C DDC Fast Speed SCL High Level Control Register 0
  • I2cmFsSclHcnt1Addr
    I2CM_FS_SCL_HCNT_1_ADDR (rw) register accessor: I2C DDC Fast Speed SCL High Level Control Register 1
  • I2cmFsSclLcnt0Addr
    I2CM_FS_SCL_LCNT_0_ADDR (rw) register accessor: I2C DDC Fast Speed SCL Low Level Control Register 0
  • I2cmFsSclLcnt1Addr
    I2CM_FS_SCL_LCNT_1_ADDR (rw) register accessor: I2C DDC Fast Speed SCL Low Level Control Register 1
  • I2cmInt
    I2CM_INT (rw) register accessor: I2C DDC Done Interrupt Register This register configures the I2C master
  • I2cmOperation
    I2CM_OPERATION (w) register accessor: I2C DDC RD/RD_EXT/WR Operation Register
  • I2cmReadBuff0
    I2CM_READ_BUFF0 (r) register accessor: I2C Master Sequential Read Buffer Register 0
  • I2cmReadBuff1
    I2CM_READ_BUFF1 (r) register accessor: I2C Master Sequential Read Buffer Register 1
  • I2cmReadBuff2
    I2CM_READ_BUFF2 (r) register accessor: I2C Master Sequential Read Buffer Register 2
  • I2cmReadBuff3
    I2CM_READ_BUFF3 (r) register accessor: I2C Master Sequential Read Buffer Register 3
  • I2cmReadBuff4
    I2CM_READ_BUFF4 (r) register accessor: I2C Master Sequential Read Buffer Register 4
  • I2cmReadBuff5
    I2CM_READ_BUFF5 (r) register accessor: I2C Master Sequential Read Buffer Register 5
  • I2cmReadBuff6
    I2CM_READ_BUFF6 (r) register accessor: I2C Master Sequential Read Buffer Register 6
  • I2cmReadBuff7
    I2CM_READ_BUFF7 (r) register accessor: I2C Master Sequential Read Buffer Register 7
  • I2cmScdcReadUpdate
    I2CM_SCDC_READ_UPDATE (rw) register accessor: SCDC Control Register
  • I2cmScdcUpdate0
    I2CM_SCDC_UPDATE0 (r) register accessor: I2C SCDC Read Update Register 0
  • I2cmScdcUpdate1
    I2CM_SCDC_UPDATE1 (r) register accessor: I2C SCDC Read Update Register 1
  • I2cmSdaHold
    I2CM_SDA_HOLD (rw) register accessor: I2C DDC SDA Hold Register
  • I2cmSegaddr
    I2CM_SEGADDR (rw) register accessor: I2C DDC Segment Address Configuration Register
  • I2cmSegptr
    I2CM_SEGPTR (rw) register accessor: I2C DDC Segment Pointer Register
  • I2cmSlave
    I2CM_SLAVE (rw) register accessor: I2C DDC Slave address Configuration Register
  • I2cmSoftrstz
    I2CM_SOFTRSTZ (rw) register accessor: I2C DDC Software Reset Control Register This register resets the I2C master.
  • I2cmSsSclHcnt0Addr
    I2CM_SS_SCL_HCNT_0_ADDR (rw) register accessor: I2C DDC Slow Speed SCL High Level Control Register 0
  • I2cmSsSclHcnt1Addr
    I2CM_SS_SCL_HCNT_1_ADDR (rw) register accessor: I2C DDC Slow Speed SCL High Level Control Register 1
  • I2cmSsSclLcnt0Addr
    I2CM_SS_SCL_LCNT_0_ADDR (rw) register accessor: I2C DDC Slow Speed SCL Low Level Control Register 0
  • I2cmSsSclLcnt1Addr
    I2CM_SS_SCL_LCNT_1_ADDR (rw) register accessor: I2C DDC Slow Speed SCL Low Level Control Register 1
  • IhAhbdmaaudStat0
    IH_AHBDMAAUD_STAT0 (rw) register accessor: AHB Audio DMA Interrupt Status Register (Functional Operation, Buffer Full
  • IhAsStat0
    IH_AS_STAT0 (rw) register accessor: Audio Sampler Interrupt Status Register (FIFO Threshold, Underflow and
  • IhCecStat0
    IH_CEC_STAT0 (rw) register accessor: CEC Interrupt Status Register (Functional Operation Interrupts)
  • IhDecode
    IH_DECODE (r) register accessor: Interruption Handler Decode Assist Register
  • IhFcStat0
    IH_FC_STAT0 (rw) register accessor: Frame Composer Interrupt Status Register 0 (Packet Interrupts)
  • IhFcStat1
    IH_FC_STAT1 (rw) register accessor: Frame Composer Interrupt Status Register 1 (Packet Interrupts)
  • IhFcStat2
    IH_FC_STAT2 (rw) register accessor: Frame Composer Interrupt Status Register 2 (Packet Interrupts)
  • IhI2cmStat0
    IH_I2CM_STAT0 (rw) register accessor: E-DDC I2C Master Interrupt Status Register (Done and Error Interrupts)
  • IhI2cmphyStat0
    IH_I2CMPHY_STAT0 (rw) register accessor: PHY GEN2 I2C Master Interrupt Status Register (Done and Error Interrupts)
  • IhMute
    IH_MUTE (rw) register accessor: Global Interrupt Mute Control Register
  • IhMuteAhbdmaaudStat0
    IH_MUTE_AHBDMAAUD_STAT0 (rw) register accessor: AHB Audio DMA Interrupt Mute Control Register
  • IhMuteAsStat0
    IH_MUTE_AS_STAT0 (rw) register accessor: Audio Sampler Interrupt Mute Control Register
  • IhMuteCecStat0
    IH_MUTE_CEC_STAT0 (rw) register accessor: CEC Interrupt Mute Control Register
  • IhMuteFcStat0
    IH_MUTE_FC_STAT0 (rw) register accessor: Frame Composer Interrupt Mute Control Register 0
  • IhMuteFcStat1
    IH_MUTE_FC_STAT1 (rw) register accessor: Frame Composer Interrupt Mute Control Register 1
  • IhMuteFcStat2
    IH_MUTE_FC_STAT2 (rw) register accessor: Frame Composer Interrupt Mute Control Register 2
  • IhMuteI2cmStat0
    IH_MUTE_I2CM_STAT0 (rw) register accessor: E-DDC I2C Master Interrupt Mute Control Register
  • IhMuteI2cmphyStat0
    IH_MUTE_I2CMPHY_STAT0 (rw) register accessor: PHY GEN2 I2C Master Interrupt Mute Control Register
  • IhMutePhyStat0
    IH_MUTE_PHY_STAT0 (rw) register accessor: PHY Interface Interrupt Mute Control Register
  • IhMuteVpStat0
    IH_MUTE_VP_STAT0 (rw) register accessor: Video Packetizer Interrupt Mute Control Register
  • IhPhyStat0
    IH_PHY_STAT0 (rw) register accessor: PHY Interface Interrupt Status Register (RXSENSE, PLL Lock and HPD
  • IhVpStat0
    IH_VP_STAT0 (rw) register accessor: Video Packetizer Interrupt Status Register (FIFO Full and Empty Interrupts)
  • JtagPhyAddr
    JTAG_PHY_ADDR (rw) register accessor: PHY JTAG Address Control Register
  • JtagPhyConfig
    JTAG_PHY_CONFIG (rw) register accessor: PHY I2C/JTAG I/O Configuration Control Register
  • JtagPhyTapIn
    JTAG_PHY_TAP_IN (rw) register accessor: PHY JTAG TAP In Control Register
  • JtagPhyTapOut
    JTAG_PHY_TAP_OUT (r) register accessor: PHY JTAG TAP Out Control Register
  • JtagPhyTapTck
    JTAG_PHY_TAP_TCK (rw) register accessor: PHY JTAG Clock Control Register
  • McClkdis
    MC_CLKDIS (rw) register accessor: Main Controller Synchronous Clock Domain Disable Register
  • McFlowctrl
    MC_FLOWCTRL (rw) register accessor: Main Controller Feed Through Control Register
  • McHeacphyRst
    MC_HEACPHY_RST (rw) register accessor: Main Controller HEAC PHY Reset Register
  • McLockonclock
    MC_LOCKONCLOCK (rw) register accessor: Main Controller Clock Present Register
  • McLockonclock2
    MC_LOCKONCLOCK_2 (rw) register accessor: Main Controller Clock Present Register 2
  • McOpctrl
    MC_OPCTRL (rw) register accessor: Main Controller HDCP Bypass Control Register
  • McOpsts
    MC_OPSTS (r) register accessor: Main Controller Status Register
  • McPhyrstz
    MC_PHYRSTZ (rw) register accessor: Main Controller PHY Reset Register
  • McSwrstzreq
    MC_SWRSTZREQ (rw) register accessor: Main Controller Software Reset Register
  • McSwrstzreq2
    MC_SWRSTZREQ_2 (rw) register accessor: Main Controller Software Reset Register 2
  • PhyConf0
    PHY_CONF0 (rw) register accessor: PHY Configuration Register
  • PhyI2cmAddress
    PHY_I2CM_ADDRESS (rw) register accessor: PHY I2C Address Configuration Register
  • PhyI2cmCtlint
    PHY_I2CM_CTLINT (rw) register accessor: PHY I2C error Interrupt Register
  • PhyI2cmDatai0
    PHY_I2CM_DATAI_0 (r) register accessor: PHY I2C Data Read Register 0
  • PhyI2cmDatai1
    PHY_I2CM_DATAI_1 (r) register accessor: PHY I2C Data Read Register 1
  • PhyI2cmDatao0
    PHY_I2CM_DATAO_0 (rw) register accessor: PHY I2C Data Write Register 0
  • PhyI2cmDatao1
    PHY_I2CM_DATAO_1 (rw) register accessor: PHY I2C Data Write Register 1
  • PhyI2cmDiv
    PHY_I2CM_DIV (rw) register accessor: PHY I2C Speed control Register
  • PhyI2cmFsSclHcnt0Addr
    PHY_I2CM_FS_SCL_HCNT_0_ADDR (rw) register accessor: PHY I2C Fast Speed SCL High Level Control Register 0
  • PhyI2cmFsSclHcnt1Addr
    PHY_I2CM_FS_SCL_HCNT_1_ADDR (rw) register accessor: PHY I2C Fast Speed SCL High Level Control Register 1
  • PhyI2cmFsSclLcnt0Addr
    PHY_I2CM_FS_SCL_LCNT_0_ADDR (rw) register accessor: PHY I2C Fast Speed SCL Low Level Control Register 0
  • PhyI2cmFsSclLcnt1Addr
    PHY_I2CM_FS_SCL_LCNT_1_ADDR (rw) register accessor: PHY I2C Fast Speed SCL Low Level Control Register 1
  • PhyI2cmInt
    PHY_I2CM_INT (rw) register accessor: PHY I2C Done Interrupt Register
  • PhyI2cmOperation
    PHY_I2CM_OPERATION (w) register accessor: PHY I2C RD/RD_EXT/WR Operation Register
  • PhyI2cmSdaHold
    PHY_I2CM_SDA_HOLD (rw) register accessor: PHY I2C SDA HOLD Control Register
  • PhyI2cmSlave
    PHY_I2CM_SLAVE (rw) register accessor: PHY I2C Slave Address Configuration Register
  • PhyI2cmSoftrstz
    PHY_I2CM_SOFTRSTZ (rw) register accessor: PHY I2C SW reset control register
  • PhyI2cmSsSclHcnt0Addr
    PHY_I2CM_SS_SCL_HCNT_0_ADDR (rw) register accessor: PHY I2C Slow Speed SCL High Level Control Register 0
  • PhyI2cmSsSclHcnt1Addr
    PHY_I2CM_SS_SCL_HCNT_1_ADDR (rw) register accessor: PHY I2C Slow Speed SCL High Level Control Register 1
  • PhyI2cmSsSclLcnt0Addr
    PHY_I2CM_SS_SCL_LCNT_0_ADDR (rw) register accessor: PHY I2C Slow Speed SCL Low Level Control Register 0
  • PhyI2cmSsSclLcnt1Addr
    PHY_I2CM_SS_SCL_LCNT_1_ADDR (rw) register accessor: PHY I2C Slow Speed SCL Low Level Control Register 1
  • PhyInt0
    PHY_INT0 (r) register accessor: PHY RXSENSE, PLL Lock, and HPD Interrupt Register
  • PhyMask0
    PHY_MASK0 (rw) register accessor: PHY RXSENSE, PLL Lock, and HPD Mask Register Mask register for generation
  • PhyPclfreq0
    PHY_PCLFREQ0 (rw) register accessor: PHY Test Interface Register 0
  • PhyPclfreq1
    PHY_PCLFREQ1 (rw) register accessor: PHY Test Interface Register 1
  • PhyPllcfgfreq0
    PHY_PLLCFGFREQ0 (rw) register accessor: PHY PLL Test Interface Register 0
  • PhyPllcfgfreq1
    PHY_PLLCFGFREQ1 (rw) register accessor: PHY PLL Test Interface Register 1
  • PhyPllcfgfreq2
    PHY_PLLCFGFREQ2 (rw) register accessor: PHY PLL Test Interface Register 2
  • PhyPol0
    PHY_POL0 (rw) register accessor: PHY RXSENSE, PLL Lock, and HPD Polarity Register Polarity register for
  • PhyStat0
    PHY_STAT0 (r) register accessor: PHY RXSENSE, PLL Lock, and HPD Status Register
  • PhyTst0
    PHY_TST0 (rw) register accessor: PHY Test Interface Register 0
  • PhyTst1
    PHY_TST1 (rw) register accessor: PHY Test Interface Register 1
  • PhyTst2
    PHY_TST2 (r) register accessor: PHY Test Interface Register 2
  • ProductId0
    PRODUCT_ID0 (r) register accessor: Product Identification Register 0
  • ProductId1
    PRODUCT_ID1 (r) register accessor: Product Identification Register 1
  • RevisionId
    REVISION_ID (r) register accessor: Revision Identification Register
  • TxBcbdata0
    TX_BCBDATA0 (rw) register accessor: Video Input bcb Data Channel Stuffing Register 0
  • TxBcbdata1
    TX_BCBDATA1 (rw) register accessor: Video Input bcb Data Channel Stuffing Register 1
  • TxGydata0
    TX_GYDATA0 (rw) register accessor: Video Input gy Data Channel Stuffing Register 0
  • TxGydata1
    TX_GYDATA1 (rw) register accessor: Video Input gy Data Channel Stuffing Register 1
  • TxInstuffing
    TX_INSTUFFING (rw) register accessor: Video Input Stuffing Enable Register
  • TxInvid0
    TX_INVID0 (rw) register accessor: Video Input Mapping and Internal Data Enable Configuration Register
  • TxRcrdata0
    TX_RCRDATA0 (rw) register accessor: Video Input rcr Data Channel Stuffing Register 0
  • TxRcrdata1
    TX_RCRDATA1 (rw) register accessor: Video Input rcr Data Channel Stuffing Register 1
  • VpConf
    VP_CONF (rw) register accessor: Video Packetizer Output and Enable Configuration Register
  • VpMask
    VP_MASK (rw) register accessor: Video Packetizer Interrupt Mask Register
  • VpPrCd
    VP_PR_CD (rw) register accessor: Video Packetizer Pixel Repetition and Color Depth Register
  • VpRemap
    VP_REMAP (rw) register accessor: Video Packetizer YCC422 Remapping Register
  • VpStatus
    VP_STATUS (r) register accessor: Video Packetizer Packing Phase Status Register
  • VpStuff
    VP_STUFF (rw) register accessor: Video Packetizer Stuffing and Default Packing Phase Register