Module rk3399_pac::dp

DisplayPort Registers

Modules

• active_line_cfg_h
  Active Line High Byte Configure Register
• active_line_cfg_l
  Active Line Low Byte Configure Register
• active_line_sta_h
  Active Line Status High Byte Register
• active_line_sta_l
  Active Line Status Low Byte Register
• active_pixel_cfg_h
  Active Pixel High Byte Configure Register
• active_pixel_cfg_l
  Active Pixel Low Byte Configure Register
• active_pixel_sta_h
  Active Pixel Status High Byte Register
• active_pixel_sta_l
  Active Pixel Status Low Byte Register
• analog_ctl_2
  Analog Control Register 2
• analog_ctl_5
  PC2 Control Register
• analog_ctl_6
  AMP_400MV_0DB
• analog_ctl_7
  AMP_600MV_0DB
• analog_ctl_8
  AMP_800MV_0DB
• analog_ctl_9
  AMP_1200MV_0DB
• analog_ctl_10
  AMP_400MV_3P5DB
• analog_ctl_11
  AMP_600MV_3P5DB
• analog_ctl_12
  AMP_800MV_3P5DB
• analog_ctl_13
  AMP_400MV_6DB
• analog_ctl_14
  AMP_600MV_6DB
• analog_ctl_15
  AMP_400MV_9DB
• analog_ctl_16
  EMP_400MV_0DB
• analog_ctl_17
  EMP_600MV_0DB
• analog_ctl_18
  EMP_800MV_0DB
• analog_ctl_19
  EMP_1200MV_0DB
• analog_ctl_20
  EMP_400MV_3P5DB
• analog_ctl_21
  EMP_600MV_3P5DB
• analog_ctl_22
  EMP_800MV_3P5DB
• analog_ctl_23
  EMP_400MV_6DB
• analog_ctl_24
  EMP_600MV_6DB
• analog_ctl_25
  EMP_400MV_9DB
• analog_ctl_26
  PC2_400MV_0DB
• analog_ctl_27
  PC2_600MV_0DB
• analog_ctl_28
  PC2_800MV_0DB
• analog_ctl_29
  PC2_1200MV_0DB
• analog_ctl_30
  PC2_400MV_3P5DB
• analog_ctl_31
  PC2_600MV_3P5DB
• analog_ctl_32
  PC2_800MV_3P5DB
• analog_ctl_33
  PC2_400MV_6DB
• analog_ctl_34
  PC2_600MV_6DB
• analog_ctl_35
  PC2_400MV_9DB
• analog_ctl_36
  CH0_AMP_FORCE_VALUE
• analog_ctl_37
  CH0_EMP_FORCE_VALUE
• analog_ctl_38
  CH0_PC2_FORCE_VALUE
• analog_ctl_39
  CH1_AMP_FORCE_VALUE
• analog_ctl_40
  CH1_EMP_FORCE_VALUE
• analog_ctl_41
  CH1_PC2_FORCE_VALUE
• analog_ctl_42
  CH0_CH1_FORCE_CTRL
• analog_ctl_43
  CH2_AMP_FORCE_VALUE
• analog_ctl_44
  CH2_EMP_FORCE_VALUE
• analog_ctl_45
  CH2_PC2_FORCE_VALUE
• analog_ctl_46
  CH3_AMP_FORCE_VALUE
• analog_ctl_47
  CH3_EMP_FORCE_VALUE
• analog_ctl_48
  CH3_PC2_FORCE_VALUE
• analog_ctl_49
  CH2_CH3_FORCE_CTRL
• ate_test_ctl
  ATE test control register
• ate_test_err_cnt
  ATE test error counter register
• ate_test_status
  ATE test status register
• aux_addr_7_0
  DP AUX CH Address Register #0
• aux_addr_15_8
  DP AUX CH Address Register #1
• aux_addr_19_16
  DP AUX CH Address Register #2
• aux_ch_ctl_1
  DP AUX Channel Control Register 1
• aux_ch_ctl_2
  DP AUX CH Control Register 2
• aux_ch_defer_ctl
  DP AUX CH DEFER Control Register
• aux_ch_sta
  AUX Channel Access Status Register
• aux_err_num
  AUX Channel Access Error Code Register
• aux_rx_comm
  DP AUX RX Command Register
• avi_db
  AVI InfoFrame Packet Data Byte
• buf_data_
  AUX CH buffer data 0 ~ 15
• buffer_data_ctl
  DP Buffer Data Count Register
• common_int_mask_1
  Common Interrupt Mask Register1
• common_int_mask_3
  Common Interrupt Mask Register3
• common_int_mask_4
  Common Interrupt Mask Register4
• common_int_sta_1
  Common Interrupt Status Register 1
• common_int_sta_3
  Common Interrupt Status Register 3
• common_int_sta_4
  Common Interrupt Status Register 4
• crc_con
  CRC control register
• dp_align_status
  DP Align Status
• dp_aux
  Aux control
• dp_bias
  Bias control
• dp_debug_ctl
  DP Debug Control Register #1
• dp_hw_link_training_ctl
  DP HW LINK TRAINING_CONTROL Register
• dp_int_sta
  DisplayPort Interrupt Status Register
• dp_int_sta_mask
  DisplayPort Interrupt enable Register
• dp_irq_vector
  DP Irq Vector
• dp_link_debug_ctl
  DP Link Debug Control Register
• dp_link_status0
  DP Lane0 and Lane1 Status
• dp_link_status1
  DP Lane2 and Lane3 Status
• dp_ln0_link_training_ctl
  DP Lane 0 Link Training Control Register
• dp_ln1_link_training_ctl
  DP Lane 1 Link Training Control Register
• dp_ln2_link_training_ctl
  DP Lane 2 Link Training Control Register
• dp_ln3_link_training_ctl
  DP Lane 3 Link Training Control Register
• dp_m_cal_ctl
  DP M Value Calculation Control Register
• dp_pd
  Power down control
• dp_reserv1
  RESERVD1
• dp_reserv2
  RESERVD2
• dp_sink_count
  DP Sink Count
• dp_sink_status
  DP Sink Status
• dp_test
  Test mode
• dp_test_80b_pattern0
  80b pattern [29:0]
• dp_test_80b_pattern1
  80b pattern [59:30]
• dp_test_80b_pattern2
  80b pattern [79:60]
• dp_test_hbr2_pattern
  Hbr2 compliance SR count
• dp_training_ptn_set
  DP Training Pattern Set Register
• dp_tx_version
  DP_TX version register
• dp_vid_ctl
  DP Video Control Register
• dp_video_fifo_thrd
  DP FIFO Threshold Register
• freq_in_reg
  freq_in_reg
• func_en_1
  Function Enable Register 1
• func_en_2
  Function Enable Register 2
• h_b_porch_cfg_h
  Horizon Back Porch High Byte Configure Register
• h_b_porch_cfg_l
  Horizon Back Porch Low Byte Configure Register
• h_b_porch_sta_h
  Horizon Back Porch Status High Byte Register
• h_b_porch_sta_l
  Horizon Back Porch Status Low Byte Register
• h_f_porch_cfg_h
  Horizon Front Porch High Byte Configure Register
• h_f_porch_cfg_l
  Horizon Front Porch Low Byte Configure Register
• h_f_porch_sta_h
  Horizon Front Porch Status High Byte Register
• h_f_porch_sta_l
  Horizon Front Porch Status Low Byte Register
• h_sync_cfg_h
  Horizon Sync Width High Byte Configure Register
• h_sync_cfg_l
  Horizon Sync Width Low Byte Configure Register
• h_sync_sta_h
  Horizon Sync Width Status High Byte Register
• h_sync_sta_l
  Horizon Sync Width Status Low Byte Register
• hpd_deglitch_h
  DP HPD De-glitch High Byte Register
• hpd_deglitch_l
  DP HPD De-glitch Low Byte Register
• if_pkt_db
  InfoFrame Packet Data Byte
• if_type
  InfoFrame Packet Type Code.
• int_ctl
  Interrupt Control Register
• int_state_0
  Debug Register
• int_state_1
  Interrupt Status Register
• lane_count_set
  DP Main Link Lane Number Register
• lane_map
  Lane Map Register
• link_bw_set
  Main Link Bandwidth Setting Register
• link_policy
  Dp Link Policy
• m_vid_0
  DP M_VID Configure Register #0
• m_vid_1
  DP M_VID Configure Register #1
• m_vid_2
  DP M_VID Configure Register #2
• m_vid_gen_filter_th
  DP M_VID Value Calculation Control Register
• m_vid_mon
  DP M_VID value monitoring register
• mpeg_db
  MPEG Source InfoFrame Packet Data Byte
• n_vid_0
  DP N_VID Configure Register #0
• n_vid_1
  DP N_VID Configure Register #1
• n_vid_2
  DP N_VID Configure Register #2
• p_band_dec_reset
  reset band decoder
• p_reg_frq
  frequency counter ,digital output for debug
• p_reg_frq_count_rdy
  frequency counter ready indicator
• pkt_send_ctl
  Packet Send Control Register
• pll_reg_1
  Pll_control_1
• pll_reg_2
  Pll_control_2
• pll_reg_3
  Pll_control_3
• pll_reg_5
  Pll_control_5
• pll_reg_mac
  Pll_control_MAC
• polling_period
  DP polling period
• psr_frame_updata_ctrl
  Frame update control for PSR
• ssc_reg
  SSC control
• sys_ctl_1
  System Control Register #1
• sys_ctl_2
  System Control Register #2
• sys_ctl_3
  System Control Register #3
• sys_ctl_4
  System Control Register #4
• total_line_cfg_h
  Total Line High Byte Configure Register
• total_line_cfg_l
  Total Line Low Byte Configure Register
• total_line_sta_h
  Total Line Status High Byte Register
• total_line_sta_l
  Total Line Status Low Byte Register
• total_pixel_cfg_h
  Total Pixel High Byte Configure Register
• total_pixel_cfg_l
  Total Pixel Low Byte Configure Register
• total_pixel_sta_h
  Total Pixel Status High Byte Register
• total_pixel_sta_l
  Total Pixel Status Low
• tx_common
  Tx terminal resistor control
• tx_common2
  Tx terminal resistor control2
• tx_common3
  Tx terminal resistor control3
• v_b_porch_cfg
  Vertical Back Porch Configure Register
• v_b_porch_sta
  Vertical Back Porch Status Register
• v_f_porch_cfg
  Vertical Front Porch Configure Register
• v_f_porch_sta
  Vertical Front Porch Status Register
• v_sync_sta
  Vertical Sync Width Status Register
• v_sync_width_cfg
  Vertical Sync Width Configure Register
• video_ctl_1
  Video Control 1
• video_ctl_2
  Video Control 2
• video_ctl_3
  Video Control 3
• video_ctl_4
  Video Control 4
• video_ctl_8
  Video Control 8
• video_ctl_10
  Video Control 10
• video_status
  Video Status Register
• vsc_shadow_db
  VSC shadow data bytes 0 ~ 7
• vsc_shadow_pb
  VSC shadow parity byte 0 ~ 1

Structs

• RegisterBlock
  Register block

Type Aliases

• ActiveLineCfgH
  ACTIVE_LINE_CFG_H (rw) register accessor: Active Line High Byte Configure Register
• ActiveLineCfgL
  ACTIVE_LINE_CFG_L (rw) register accessor: Active Line Low Byte Configure Register
• ActiveLineStaH
  ACTIVE_LINE_STA_H (rw) register accessor: Active Line Status High Byte Register
• ActiveLineStaL
  ACTIVE_LINE_STA_L (rw) register accessor: Active Line Status Low Byte Register
• ActivePixelCfgH
  ACTIVE_PIXEL_CFG_H (rw) register accessor: Active Pixel High Byte Configure Register
• ActivePixelCfgL
  ACTIVE_PIXEL_CFG_L (rw) register accessor: Active Pixel Low Byte Configure Register
• ActivePixelStaH
  ACTIVE_PIXEL_STA_H (rw) register accessor: Active Pixel Status High Byte Register
• ActivePixelStaL
  ACTIVE_PIXEL_STA_L (rw) register accessor: Active Pixel Status Low Byte Register
• AnalogCtl2
  ANALOG_CTL_2 (rw) register accessor: Analog Control Register 2
• AnalogCtl5
  ANALOG_CTL_5 (rw) register accessor: PC2 Control Register
• AnalogCtl6
  ANALOG_CTL_6 (rw) register accessor: AMP_400MV_0DB
• AnalogCtl7
  ANALOG_CTL_7 (rw) register accessor: AMP_600MV_0DB
• AnalogCtl8
  ANALOG_CTL_8 (rw) register accessor: AMP_800MV_0DB
• AnalogCtl9
  ANALOG_CTL_9 (rw) register accessor: AMP_1200MV_0DB
• AnalogCtl10
  ANALOG_CTL_10 (rw) register accessor: AMP_400MV_3P5DB
• AnalogCtl11
  ANALOG_CTL_11 (rw) register accessor: AMP_600MV_3P5DB
• AnalogCtl12
  ANALOG_CTL_12 (rw) register accessor: AMP_800MV_3P5DB
• AnalogCtl13
  ANALOG_CTL_13 (rw) register accessor: AMP_400MV_6DB
• AnalogCtl14
  ANALOG_CTL_14 (rw) register accessor: AMP_600MV_6DB
• AnalogCtl15
  ANALOG_CTL_15 (rw) register accessor: AMP_400MV_9DB
• AnalogCtl16
  ANALOG_CTL_16 (rw) register accessor: EMP_400MV_0DB
• AnalogCtl17
  ANALOG_CTL_17 (rw) register accessor: EMP_600MV_0DB
• AnalogCtl18
  ANALOG_CTL_18 (rw) register accessor: EMP_800MV_0DB
• AnalogCtl19
  ANALOG_CTL_19 (rw) register accessor: EMP_1200MV_0DB
• AnalogCtl20
  ANALOG_CTL_20 (rw) register accessor: EMP_400MV_3P5DB
• AnalogCtl21
  ANALOG_CTL_21 (rw) register accessor: EMP_600MV_3P5DB
• AnalogCtl22
  ANALOG_CTL_22 (rw) register accessor: EMP_800MV_3P5DB
• AnalogCtl23
  ANALOG_CTL_23 (rw) register accessor: EMP_400MV_6DB
• AnalogCtl24
  ANALOG_CTL_24 (rw) register accessor: EMP_600MV_6DB
• AnalogCtl25
  ANALOG_CTL_25 (rw) register accessor: EMP_400MV_9DB
• AnalogCtl26
  ANALOG_CTL_26 (rw) register accessor: PC2_400MV_0DB
• AnalogCtl27
  ANALOG_CTL_27 (rw) register accessor: PC2_600MV_0DB
• AnalogCtl28
  ANALOG_CTL_28 (rw) register accessor: PC2_800MV_0DB
• AnalogCtl29
  ANALOG_CTL_29 (rw) register accessor: PC2_1200MV_0DB
• AnalogCtl30
  ANALOG_CTL_30 (rw) register accessor: PC2_400MV_3P5DB
• AnalogCtl31
  ANALOG_CTL_31 (rw) register accessor: PC2_600MV_3P5DB
• AnalogCtl32
  ANALOG_CTL_32 (rw) register accessor: PC2_800MV_3P5DB
• AnalogCtl33
  ANALOG_CTL_33 (rw) register accessor: PC2_400MV_6DB
• AnalogCtl34
  ANALOG_CTL_34 (rw) register accessor: PC2_600MV_6DB
• AnalogCtl35
  ANALOG_CTL_35 (rw) register accessor: PC2_400MV_9DB
• AnalogCtl36
  ANALOG_CTL_36 (rw) register accessor: CH0_AMP_FORCE_VALUE
• AnalogCtl37
  ANALOG_CTL_37 (rw) register accessor: CH0_EMP_FORCE_VALUE
• AnalogCtl38
  ANALOG_CTL_38 (rw) register accessor: CH0_PC2_FORCE_VALUE
• AnalogCtl39
  ANALOG_CTL_39 (rw) register accessor: CH1_AMP_FORCE_VALUE
• AnalogCtl40
  ANALOG_CTL_40 (rw) register accessor: CH1_EMP_FORCE_VALUE
• AnalogCtl41
  ANALOG_CTL_41 (rw) register accessor: CH1_PC2_FORCE_VALUE
• AnalogCtl42
  ANALOG_CTL_42 (rw) register accessor: CH0_CH1_FORCE_CTRL
• AnalogCtl43
  ANALOG_CTL_43 (rw) register accessor: CH2_AMP_FORCE_VALUE
• AnalogCtl44
  ANALOG_CTL_44 (rw) register accessor: CH2_EMP_FORCE_VALUE
• AnalogCtl45
  ANALOG_CTL_45 (rw) register accessor: CH2_PC2_FORCE_VALUE
• AnalogCtl46
  ANALOG_CTL_46 (rw) register accessor: CH3_AMP_FORCE_VALUE
• AnalogCtl47
  ANALOG_CTL_47 (rw) register accessor: CH3_EMP_FORCE_VALUE
• AnalogCtl48
  ANALOG_CTL_48 (rw) register accessor: CH3_PC2_FORCE_VALUE
• AnalogCtl49
  ANALOG_CTL_49 (rw) register accessor: CH2_CH3_FORCE_CTRL
• AteTestCtl
  ATE_TEST_CTL (rw) register accessor: ATE test control register
• AteTestErrCnt
  ATE_TEST_ERR_CNT (rw) register accessor: ATE test error counter register
• AteTestStatus
  ATE_TEST_STATUS (rw) register accessor: ATE test status register
• AuxAddr7_0
  AUX_ADDR_7_0 (rw) register accessor: DP AUX CH Address Register #0
• AuxAddr15_8
  AUX_ADDR_15_8 (rw) register accessor: DP AUX CH Address Register #1
• AuxAddr19_16
  AUX_ADDR_19_16 (rw) register accessor: DP AUX CH Address Register #2
• AuxChCtl1
  AUX_CH_CTL_1 (rw) register accessor: DP AUX Channel Control Register 1
• AuxChCtl2
  AUX_CH_CTL_2 (rw) register accessor: DP AUX CH Control Register 2
• AuxChDeferCtl
  AUX_CH_DEFER_CTL (rw) register accessor: DP AUX CH DEFER Control Register
• AuxChSta
  AUX_CH_STA (rw) register accessor: AUX Channel Access Status Register
• AuxErrNum
  AUX_ERR_NUM (rw) register accessor: AUX Channel Access Error Code Register
• AuxRxComm
  AUX_RX_COMM (rw) register accessor: DP AUX RX Command Register
• AviDb
  AVI_DB (rw) register accessor: AVI InfoFrame Packet Data Byte
• BufData_
  BUF_DATA_ (rw) register accessor: AUX CH buffer data 0 ~ 15
• BufferDataCtl
  BUFFER_DATA_CTL (rw) register accessor: DP Buffer Data Count Register
• CommonIntMask1
  COMMON_INT_MASK_1 (rw) register accessor: Common Interrupt Mask Register1
• CommonIntMask3
  COMMON_INT_MASK_3 (rw) register accessor: Common Interrupt Mask Register3
• CommonIntMask4
  COMMON_INT_MASK_4 (rw) register accessor: Common Interrupt Mask Register4
• CommonIntSta1
  COMMON_INT_STA_1 (rw) register accessor: Common Interrupt Status Register 1
• CommonIntSta3
  COMMON_INT_STA_3 (rw) register accessor: Common Interrupt Status Register 3
• CommonIntSta4
  COMMON_INT_STA_4 (rw) register accessor: Common Interrupt Status Register 4
• CrcCon
  CRC_CON (rw) register accessor: CRC control register
• DpAlignStatus
  DP_ALIGN_STATUS (rw) register accessor: DP Align Status
• DpAux
  DP_AUX (rw) register accessor: Aux control
• DpBias
  DP_BIAS (rw) register accessor: Bias control
• DpDebugCtl
  DP_DEBUG_CTL (rw) register accessor: DP Debug Control Register #1
• DpHwLinkTrainingCtl
  DP_HW_LINK_TRAINING_CTL (rw) register accessor: DP HW LINK TRAINING_CONTROL Register
• DpIntSta
  DP_INT_STA (rw) register accessor: DisplayPort Interrupt Status Register
• DpIntStaMask
  DP_INT_STA_MASK (rw) register accessor: DisplayPort Interrupt enable Register
• DpIrqVector
  DP_IRQ_VECTOR (rw) register accessor: DP Irq Vector
• DpLinkDebugCtl
  DP_LINK_DEBUG_CTL (rw) register accessor: DP Link Debug Control Register
• DpLinkStatus0
  DP_LINK_STATUS0 (rw) register accessor: DP Lane0 and Lane1 Status
• DpLinkStatus1
  DP_LINK_STATUS1 (rw) register accessor: DP Lane2 and Lane3 Status
• DpLn0LinkTrainingCtl
  DP_LN0_LINK_TRAINING_CTL (rw) register accessor: DP Lane 0 Link Training Control Register
• DpLn1LinkTrainingCtl
  DP_LN1_LINK_TRAINING_CTL (rw) register accessor: DP Lane 1 Link Training Control Register
• DpLn2LinkTrainingCtl
  DP_LN2_LINK_TRAINING_CTL (rw) register accessor: DP Lane 2 Link Training Control Register
• DpLn3LinkTrainingCtl
  DP_LN3_LINK_TRAINING_CTL (rw) register accessor: DP Lane 3 Link Training Control Register
• DpMCalCtl
  DP_M_CAL_CTL (rw) register accessor: DP M Value Calculation Control Register
• DpPd
  DP_PD (rw) register accessor: Power down control
• DpReserv1
  DP_RESERV1 (rw) register accessor: RESERVD1
• DpReserv2
  DP_RESERV2 (rw) register accessor: RESERVD2
• DpSinkCount
  DP_SINK_COUNT (rw) register accessor: DP Sink Count
• DpSinkStatus
  DP_SINK_STATUS (rw) register accessor: DP Sink Status
• DpTest
  DP_TEST (rw) register accessor: Test mode
• DpTest80bPattern0
  DP_TEST_80B_PATTERN0 (rw) register accessor: 80b pattern [29:0]
• DpTest80bPattern1
  DP_TEST_80B_PATTERN1 (rw) register accessor: 80b pattern [59:30]
• DpTest80bPattern2
  DP_TEST_80B_PATTERN2 (rw) register accessor: 80b pattern [79:60]
• DpTestHbr2Pattern
  DP_TEST_HBR2_PATTERN (rw) register accessor: Hbr2 compliance SR count
• DpTrainingPtnSet
  DP_TRAINING_PTN_SET (rw) register accessor: DP Training Pattern Set Register
• DpTxVersion
  DP_TX_VERSION (rw) register accessor: DP_TX version register
• DpVidCtl
  DP_VID_CTL (rw) register accessor: DP Video Control Register
• DpVideoFifoThrd
  DP_VIDEO_FIFO_THRD (rw) register accessor: DP FIFO Threshold Register
• FreqInReg
  FREQ_IN_REG (rw) register accessor: freq_in_reg
• FuncEn1
  FUNC_EN_1 (rw) register accessor: Function Enable Register 1
• FuncEn2
  FUNC_EN_2 (rw) register accessor: Function Enable Register 2
• HBPorchCfgH
  H_B_PORCH_CFG_H (rw) register accessor: Horizon Back Porch High Byte Configure Register
• HBPorchCfgL
  H_B_PORCH_CFG_L (rw) register accessor: Horizon Back Porch Low Byte Configure Register
• HBPorchStaH
  H_B_PORCH_STA_H (rw) register accessor: Horizon Back Porch Status High Byte Register
• HBPorchStaL
  H_B_PORCH_STA_L (rw) register accessor: Horizon Back Porch Status Low Byte Register
• HFPorchCfgH
  H_F_PORCH_CFG_H (rw) register accessor: Horizon Front Porch High Byte Configure Register
• HFPorchCfgL
  H_F_PORCH_CFG_L (rw) register accessor: Horizon Front Porch Low Byte Configure Register
• HFPorchStaH
  H_F_PORCH_STA_H (rw) register accessor: Horizon Front Porch Status High Byte Register
• HFPorchStaL
  H_F_PORCH_STA_L (rw) register accessor: Horizon Front Porch Status Low Byte Register
• HSyncCfgH
  H_SYNC_CFG_H (rw) register accessor: Horizon Sync Width High Byte Configure Register
• HSyncCfgL
  H_SYNC_CFG_L (rw) register accessor: Horizon Sync Width Low Byte Configure Register
• HSyncStaH
  H_SYNC_STA_H (rw) register accessor: Horizon Sync Width Status High Byte Register
• HSyncStaL
  H_SYNC_STA_L (rw) register accessor: Horizon Sync Width Status Low Byte Register
• HpdDeglitchH
  HPD_DEGLITCH_H (rw) register accessor: DP HPD De-glitch High Byte Register
• HpdDeglitchL
  HPD_DEGLITCH_L (rw) register accessor: DP HPD De-glitch Low Byte Register
• IfPktDb
  IF_PKT_DB (rw) register accessor: InfoFrame Packet Data Byte
• IfType
  IF_TYPE (rw) register accessor: InfoFrame Packet Type Code.
• IntCtl
  INT_CTL (rw) register accessor: Interrupt Control Register
• IntState0
  INT_STATE_0 (rw) register accessor: Debug Register
• IntState1
  INT_STATE_1 (rw) register accessor: Interrupt Status Register
• LaneCountSet
  LANE_COUNT_SET (rw) register accessor: DP Main Link Lane Number Register
• LaneMap
  LANE_MAP (rw) register accessor: Lane Map Register
• LinkBwSet
  LINK_BW_SET (rw) register accessor: Main Link Bandwidth Setting Register
• LinkPolicy
  LINK_POLICY (rw) register accessor: Dp Link Policy
• MVid0
  M_VID_0 (rw) register accessor: DP M_VID Configure Register #0
• MVid1
  M_VID_1 (rw) register accessor: DP M_VID Configure Register #1
• MVid2
  M_VID_2 (rw) register accessor: DP M_VID Configure Register #2
• MVidGenFilterTh
  M_VID_GEN_FILTER_TH (rw) register accessor: DP M_VID Value Calculation Control Register
• MVidMon
  M_VID_MON (rw) register accessor: DP M_VID value monitoring register
• MpegDb
  MPEG_DB (rw) register accessor: MPEG Source InfoFrame Packet Data Byte
• NVid0
  N_VID_0 (rw) register accessor: DP N_VID Configure Register #0
• NVid1
  N_VID_1 (rw) register accessor: DP N_VID Configure Register #1
• NVid2
  N_VID_2 (rw) register accessor: DP N_VID Configure Register #2
• PBandDecReset
  P_BAND_DEC_RESET (rw) register accessor: reset band decoder
• PRegFrq
  P_REG_FRQ (rw) register accessor: frequency counter ,digital output for debug
• PRegFrqCountRdy
  P_REG_FRQ_COUNT_RDY (rw) register accessor: frequency counter ready indicator
• PktSendCtl
  PKT_SEND_CTL (rw) register accessor: Packet Send Control Register
• PllReg1
  PLL_REG_1 (rw) register accessor: Pll_control_1
• PllReg2
  PLL_REG_2 (rw) register accessor: Pll_control_2
• PllReg3
  PLL_REG_3 (rw) register accessor: Pll_control_3
• PllReg5
  PLL_REG_5 (rw) register accessor: Pll_control_5
• PllRegMac
  PLL_REG_MAC (rw) register accessor: Pll_control_MAC
• PollingPeriod
  POLLING_PERIOD (rw) register accessor: DP polling period
• PsrFrameUpdataCtrl
  PSR_FRAME_UPDATA_CTRL (rw) register accessor: Frame update control for PSR
• SscReg
  SSC_REG (rw) register accessor: SSC control
• SysCtl1
  SYS_CTL_1 (rw) register accessor: System Control Register #1
• SysCtl2
  SYS_CTL_2 (rw) register accessor: System Control Register #2
• SysCtl3
  SYS_CTL_3 (rw) register accessor: System Control Register #3
• SysCtl4
  SYS_CTL_4 (rw) register accessor: System Control Register #4
• TotalLineCfgH
  TOTAL_LINE_CFG_H (rw) register accessor: Total Line High Byte Configure Register
• TotalLineCfgL
  TOTAL_LINE_CFG_L (rw) register accessor: Total Line Low Byte Configure Register
• TotalLineStaH
  TOTAL_LINE_STA_H (rw) register accessor: Total Line Status High Byte Register
• TotalLineStaL
  TOTAL_LINE_STA_L (rw) register accessor: Total Line Status Low Byte Register
• TotalPixelCfgH
  TOTAL_PIXEL_CFG_H (rw) register accessor: Total Pixel High Byte Configure Register
• TotalPixelCfgL
  TOTAL_PIXEL_CFG_L (rw) register accessor: Total Pixel Low Byte Configure Register
• TotalPixelStaH
  TOTAL_PIXEL_STA_H (rw) register accessor: Total Pixel Status High Byte Register
• TotalPixelStaL
  TOTAL_PIXEL_STA_L (rw) register accessor: Total Pixel Status Low
• TxCommon
  TX_COMMON (rw) register accessor: Tx terminal resistor control
• TxCommon2
  TX_COMMON2 (rw) register accessor: Tx terminal resistor control2
• TxCommon3
  TX_COMMON3 (rw) register accessor: Tx terminal resistor control3
• VBPorchCfg
  V_B_PORCH_CFG (rw) register accessor: Vertical Back Porch Configure Register
• VBPorchSta
  V_B_PORCH_STA (rw) register accessor: Vertical Back Porch Status Register
• VFPorchCfg
  V_F_PORCH_CFG (rw) register accessor: Vertical Front Porch Configure Register
• VFPorchSta
  V_F_PORCH_STA (rw) register accessor: Vertical Front Porch Status Register
• VSyncSta
  V_SYNC_STA (rw) register accessor: Vertical Sync Width Status Register
• VSyncWidthCfg
  V_SYNC_WIDTH_CFG (rw) register accessor: Vertical Sync Width Configure Register
• VideoCtl1
  VIDEO_CTL_1 (rw) register accessor: Video Control 1
• VideoCtl2
  VIDEO_CTL_2 (rw) register accessor: Video Control 2
• VideoCtl3
  VIDEO_CTL_3 (rw) register accessor: Video Control 3
• VideoCtl4
  VIDEO_CTL_4 (rw) register accessor: Video Control 4
• VideoCtl8
  VIDEO_CTL_8 (rw) register accessor: Video Control 8
• VideoCtl10
  VIDEO_CTL_10 (rw) register accessor: Video Control 10
• VideoStatus
  VIDEO_STATUS (rw) register accessor: Video Status Register
• VscShadowDb
  VSC_SHADOW_DB (rw) register accessor: VSC shadow data bytes 0 ~ 7
• VscShadowPb
  VSC_SHADOW_PB (rw) register accessor: VSC shadow parity byte 0 ~ 1