Module rk3399_pac::ddr_mon

DDR Monitor (DDR_MON) Registers

Modules

• ch0_count_num
  Channel 0 Timer Count Number
• ch0_ddr_fifo0_addr
  DDR Channel 0 Controller Interface Address FIFO0
• ch0_ddr_fifo1_addr
  DDR Channel 0 Controller Interface Address FIFO1
• ch0_ddr_fifo2_addr
  DDR Channel 0 Controller Interface Address FIFO2
• ch0_ddr_fifo3_addr
  DDR Channel 0 Controller Interface Address FIFO3
• ch0_dfi_access_num
  Channel 0 DFI Read and Write Command Number
• ch0_dfi_act_num
  Channel 0 DFI Active Command Number
• ch0_dfi_rd_num
  Channel 0 DFI read Command Number
• ch0_dfi_wr_num
  Channel 0 DFI write Command Number
• ch0_rd_end_addr
  Channel 0 Read End Address
• ch0_rd_start_addr
  Channel 0 Read Start Address
• ch0_wr_end_addr
  Channel 0 Write End Address
• ch0_wr_start_addr
  Channel 0 Write Start Address
• ch1_count_num
  Channel 1 Timer Count Number
• ch1_ddr_fifo0_addr
  DDR Channel 1 Controller Interface Address FIFO0
• ch1_ddr_fifo1_addr
  DDR Channel 1 Controller Interface Address FIFO1
• ch1_ddr_fifo2_addr
  DDR Channel 1 Controller Interface Address FIFO2
• ch1_ddr_fifo3_addr
  DDR Channel 1 Controller Interface Address FIFO3
• ch1_dfi_access_num
  Channel 1 DFI Read and Write Command Number
• ch1_dfi_act_num
  Channel 1 DFI Active Command Number
• ch1_dfi_rd_num
  Channel 1 DFI read Command Number
• ch1_dfi_wr_num
  Channel 1 DFI write Command Number
• ch1_rd_end_addr
  Channel 1 Read End Address
• ch1_rd_start_addr
  Channel 1 Read Start Address
• ch1_wr_end_addr
  Channel 1 Write End Address
• ch1_wr_start_addr
  Channel 1 Write Start Address
• ctrl
  DDR Monitor Control Register
• ddr_if_ctrl
  DDR interface Control Register
• floor_number
  The Low Threshold in the Comparison of DDR Access
• int_mask
  Interrupt mask control
• int_status
  Interrupt Status
• ip_version
  DDR Monitor IP Version
• timer_count
  The DFI Timer Threshold
• top_number
  The High Threshold in the Comparison of DDR Access

Structs

• RegisterBlock
  Register block

Type Aliases

• Ch0CountNum
  CH0_COUNT_NUM (r) register accessor: Channel 0 Timer Count Number
• Ch0DdrFifo0Addr
  CH0_DDR_FIFO0_ADDR (r) register accessor: DDR Channel 0 Controller Interface Address FIFO0
• Ch0DdrFifo1Addr
  CH0_DDR_FIFO1_ADDR (r) register accessor: DDR Channel 0 Controller Interface Address FIFO1
• Ch0DdrFifo2Addr
  CH0_DDR_FIFO2_ADDR (r) register accessor: DDR Channel 0 Controller Interface Address FIFO2
• Ch0DdrFifo3Addr
  CH0_DDR_FIFO3_ADDR (r) register accessor: DDR Channel 0 Controller Interface Address FIFO3
• Ch0DfiAccessNum
  CH0_DFI_ACCESS_NUM (r) register accessor: Channel 0 DFI Read and Write Command Number
• Ch0DfiActNum
  CH0_DFI_ACT_NUM (r) register accessor: Channel 0 DFI Active Command Number
• Ch0DfiRdNum
  CH0_DFI_RD_NUM (r) register accessor: Channel 0 DFI read Command Number
• Ch0DfiWrNum
  CH0_DFI_WR_NUM (r) register accessor: Channel 0 DFI write Command Number
• Ch0RdEndAddr
  CH0_RD_END_ADDR (rw) register accessor: Channel 0 Read End Address
• Ch0RdStartAddr
  CH0_RD_START_ADDR (rw) register accessor: Channel 0 Read Start Address
• Ch0WrEndAddr
  CH0_WR_END_ADDR (rw) register accessor: Channel 0 Write End Address
• Ch0WrStartAddr
  CH0_WR_START_ADDR (rw) register accessor: Channel 0 Write Start Address
• Ch1CountNum
  CH1_COUNT_NUM (r) register accessor: Channel 1 Timer Count Number
• Ch1DdrFifo0Addr
  CH1_DDR_FIFO0_ADDR (r) register accessor: DDR Channel 1 Controller Interface Address FIFO0
• Ch1DdrFifo1Addr
  CH1_DDR_FIFO1_ADDR (r) register accessor: DDR Channel 1 Controller Interface Address FIFO1
• Ch1DdrFifo2Addr
  CH1_DDR_FIFO2_ADDR (r) register accessor: DDR Channel 1 Controller Interface Address FIFO2
• Ch1DdrFifo3Addr
  CH1_DDR_FIFO3_ADDR (r) register accessor: DDR Channel 1 Controller Interface Address FIFO3
• Ch1DfiAccessNum
  CH1_DFI_ACCESS_NUM (r) register accessor: Channel 1 DFI Read and Write Command Number
• Ch1DfiActNum
  CH1_DFI_ACT_NUM (r) register accessor: Channel 1 DFI Active Command Number
• Ch1DfiRdNum
  CH1_DFI_RD_NUM (r) register accessor: Channel 1 DFI read Command Number
• Ch1DfiWrNum
  CH1_DFI_WR_NUM (r) register accessor: Channel 1 DFI write Command Number
• Ch1RdEndAddr
  CH1_RD_END_ADDR (rw) register accessor: Channel 1 Read End Address
• Ch1RdStartAddr
  CH1_RD_START_ADDR (rw) register accessor: Channel 1 Read Start Address
• Ch1WrEndAddr
  CH1_WR_END_ADDR (rw) register accessor: Channel 1 Write End Address
• Ch1WrStartAddr
  CH1_WR_START_ADDR (rw) register accessor: Channel 1 Write Start Address
• Ctrl
  CTRL (rw) register accessor: DDR Monitor Control Register
• DdrIfCtrl
  DDR_IF_CTRL (rw) register accessor: DDR interface Control Register
• FloorNumber
  FLOOR_NUMBER (r) register accessor: The Low Threshold in the Comparison of DDR Access
• IntMask
  INT_MASK (rw) register accessor: Interrupt mask control
• IntStatus
  INT_STATUS (r) register accessor: Interrupt Status
• IpVersion
  IP_VERSION (r) register accessor: DDR Monitor IP Version
• TimerCount
  TIMER_COUNT (r) register accessor: The DFI Timer Threshold
• TopNumber
  TOP_NUMBER (r) register accessor: The High Threshold in the Comparison of DDR Access